Update the ti-dm firmware to 09.01.02 for Jacinto devices.

These were generated using SYSFW v09.01.02

J7200
Enable ARM to change PLL VCO frequency
Provide support for S2R

J721E
Enable ARM to change PLL VCO frequency

J721S2
Add virtual device to control SEL_EXTWAVE mux
Enable ARM dynamic frequency change

J784S4
Add virtual device to control SEL_EXTWAVE mux
Enable ARM dynamic frequency change

MD5 Checksum:
d85de7f0bd3677085858f40ef41956b1  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
82b4dd47fe2e4edf28b3a6e2bb95bc01  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
582796c7602ce4b228cb729dc610bd00  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
599f972f43c0210b36912c087e5b2039  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

Update the following ti-dm firmware
- REL.MCUSDK.09.00.01.15 for am62x, am62ax and am62px

Major changes compared to previous version:
- Additional Klocwork MISRA-C issues addressed
- Fix junk value returned for get_fw_caps
- PLL driver update for checking divider option before changing VCO
- LPM: Added support for memory based traces as an option
- LPM: DDR sequence update to cover for LPDDR
- LPM: Disable PLLs fully in sleep path instead of leaving it at bypass

MD5 Checksum:
2eea4a2f0d52e473ff3e562cac41cc76  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
27f10266d01ae3b69045d8cb8ed7840a  ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f
c2b16b70f0ef17a142155f9d7f2b42ed  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the ti-dm firmware to 09.01.00 for Jacinto devices.

These were generated using SYSFW v09.01.00

J7200
Fix MSMC clock to 1GHz
Fix MISRA C violations
Fix Main domain reset wait condition
Fix DSS set frequency

J721E
Fix DSS set frequency
Fix MISRA C violations
Fix Main domain reset wait condition

J721S2
Add virtual device odd numbered timers
Add mising IR rom usage mapping
Fix DSS set frequency
Fix MISRA C violations
Fix Main domain reset wait condition

J784S4
Add virtual device odd numbered timers
Add mising IR rom usage mapping
Fix DSS set frequency
Fix MISRA C violations
Fix Main domain reset wait condition

MD5 Checksum:
65cd5503060a481cdc2f9836d29a5b34  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
ae9a386d3ce26ac6064bf047eb681e25  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
084a9bf64fa13f749a76629cbabfae43  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
ff2f7c108ba002c4f921ef72ba2dae5d  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

Update the ti-dm firmware to 09.00.06a for J7200 device.

Major Changes compared to 09.00.06 :
    -Fix stream benchmark performance drop by setting the frequency
     of MSMC clock to 1GHz in DM

MD5 Checksum:
61c40fb4ff175c48681e73914a7fc217  ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

Update the ti-dm firmware to 09.00.06 for Jacinto devices.

These were generated using SYSFW v09.00.06

j7200
Remove modify_parent_frequency flag for PLL8
Add support to handle firewall exception

J721E
Remove modify_parent_frequency flag for PLL8

J721S2
Add DSMEK Support
Add support to handle firewall exception

J784S4
Add DSMEK Support
Add support to handle firewall exception

MD5 Checksum:
1ada45a788d0d02defa09123dac515b4  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
2900300d9eb02243a5bbc51619c5af65  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
4ecfa16ae460b9ebcf3ccf5a6be53e78  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
a82038bbfe2e52f1e2fa0fe02b6edd31  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

This reverts commit be9bc6e0

.

This revert was a mistake. Adding the ti-dm update to
09.00.12  version update back.

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

This reverts commit 37d80954.

Update the following ti-dm firmware
- REL.MCUSDK.09.00.00.12 for am62x
- REL.MCUSDK.09.00.00.12 for am62ax

Major changes compared to previous version:
- Klocwork MISRA-C issues addressed
- Added support for copying FS stub from DDR to TCM
- am62x: lpm: WKUP UART, WKUP I2C and WKUP DMTIMER 0/1 wakeup capability enabled
- am62x: lpm: MCU only mode supported
- am62x: lpm: MCU IPC wakeup capability enabled

MD5 Checksum:
ffa44170c99614da11e46703ca1c9e3b  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
80089fdb75a42832f4478df7272b6279  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the ti-dm firmware to 09.00.03 for Jacinto devices.

These were generated using SYSFW v09.00.03

J721E:
support ACSPCIE mux clocking option
Enable Change parent freq flag for PLL8

J7200:
Enable NO_HW_REINIT for MSMC clock
Enable Change parent freq flag for PLL8

J721S2:
Update General purpose interrupt index for Ring
accelerator

J784S4:
open firewall for BOLT on PSC device.
Update General purpose interrupt index for Ring
accelerator

General:
Open firewalls for compare event router
Enable maximum possible PROC_AUTH_BOOT performance for authentication

MD5 Checksum:
e78b737398f143db5030f55cc9050950  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
89d934656bff38074f1389ea5d4b4abc  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
5cdf3ebb8d36cf304772baa024709c92  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
00b1659c28bdf69961e16915fb00570c  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

Update the following ti-dm firmware
- REL.MCUSDK.09.00.00.09 for am62x
- REL.MCUSDK.09.00.00.09 for am62ax

Major changes compared to previous version:
- rm/pm: compiler warnings addressed
- rm/pm: Klocwork static analysis issues addressed
- sciserver/dm_stub: Klocwork MISRA-C issues addressed

MD5 Checksum:
84ebad7793eef6f978db5da409ffde94  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
2e1cfa17292ec6036390b58eacdd724d  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware
- REL.MCUSDK.09.00.00.06 for am62x
- REL.MCUSDK.09.00.00.06 for am62ax

Major changes compared to previous version:
- Static Ananlysis Fixes on rm_pm_hal, self_reset and SCI components
- am62x: lpm: Enable MCU IPC wake up source
- am62a: Update default VCO frequency of DDR PLL to 933.25 MHz
- am62a: DM R5 to C7X IPC support

MD5 Checksum:
0205bab41e2662d843197ff3ac346c0d  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
200b48410ec6102d80dbaba8d5094b52  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware
- REL.MCUSDK.09.00.00.05 for am62x
- REL.MCUSDK.09.00.00.05 for am62ax

Major changes compared to previous version:
- Revert the PLL change that caused UART console regression

MD5 Checksum:
0c15724dd9d6169378fe287a1e9ab999  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
eb15e067b37da7b3c6824600bc1feb3b  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Tested-by: Dhruva Gole <d-gole@ti.com>

Update the following ti-dm firmware
- REL.MCUSDK.09.00.00.01 for am62x
- REL.MCUSDK.09.00.00.01 for am62ax

Major changes compared to previous version:
- AM62x/AM62Ax: Fix isolation LPSC
- AM62x: LPM: Fix PSC and LPSC Ids
- PLL driver updates to calculate VCO frequency
- AM62x: LPM: Fix for MCU GPIO clock source in resume path
- AM62x: LPM: Save and restore mmr lock status
- AM62x: LPM: Fix RAT configuration issue exposed by Kernel 6.1

MD5 Checksum:
8b2ffa978b2e9bb4e59c290b9b493f07  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
146d45ae5600e8ffecd3337102f71975  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Venkatesan Krishnamoorthy authored 2 years ago and Vignesh Raghavendra committed 2 years ago

Update the following ti-dm firmware
- 08.06.00.05 for am62ax (Firmware Builder)

Major changes compared to previous version:
- Generated from Firmware Builder SDK version 08.06.00.05

MD5 Checksum:
2b0de465815a3c28d2042f76a2e8e76b  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Venkatesan Krishnamoorthy <v-krishnamoorthy@ti.com>

Venkatesan Krishnamoorthy authored 2 years ago and Vignesh Raghavendra committed 2 years ago

Update the following ti-dm firmware
- 08.06.00.04 for am62ax (Firmware Builder)

Major changes compared to previous version:
- DM firmware is updated to be compatible with ti-sysfw v08.06.04

MD5 Checksum:
369b3c87e2f92e51fcab652fad1dd157  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Venkatesan Krishnamoorthy <v-krishnamoorthy@ti.com>

Update the following ti-dm firmware
- 08.06.00.03 for am62ax (Firmware Builder)

Major changes compared to previous version:
- Build from 08.06.00.03 version of Firmware Builder SDK.

MD5 Checksum:
f69e0b5142418789a3c44fbaaf832755  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Venkatesan Krishnamoorthy <v-krishnamoorthy@ti.com>

Update the following ti-dm firmware
- 08.06.00.10 for am62x (MCU+)
- 08.06.00.02 for am62ax (Firmware Builder)

Major changes compared to previous version:
- DM firmware is updated to be compatible with ti-sysfw  v08.06.03

MD5 Checksum:
24136f7a15ecb03f5df9eadad9c54d46  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f
675d1c9b0c108fa02bc3e1cf6632445f  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Venkatesan Krishnamoorthy <v-krishnamoorthy@ti.com>
[praneeth@ti.com: minor edit to fix md5sum in commitmsg]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Update the following ti-dm firmware
- 08.06.00.01 for am62ax (Firmware Builder SDK)

Major changes compared to previous version:
 - Firmware is build with VPAC, TIOVX and vision apps.
 - The RTOS IPC memory region is bumped up to 16Mb from 3Mb and dma heap
   carveout is reduced by 16 Mb to 176Mb to fit overall memory map to
   exact 1Gb
   i.e from 0x80000000 to 0xBFFFFFFF.

MD5 Checksum:
4f56eaca0661e1c7b2b0ecd2bb803a3f  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Venkatesan Krishnamoorthy <v-krishnamoorthy@ti.com>

Update the ti-dm firmware to 08.06.01a for Jacinto devices.

These were generated using SYSFW v08.06.01a

j7200
Support 2500MHz VCO frequency for MAIN PLL 3

J721E
Support 2500MHz VCO frequency for MAIN PLL 3

General
Fractional roundoff has been implemented in PLL multiplier to calculate VCO frequency.

MD5 Checksum:
98249b92f50efeb884f476906c2cfe84  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
acd3883adf0b4662c4fc9c1be79418c5  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
fa29165dd5a4179c3bb690ef55644e36  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
c22e44e6f3822a698c844b52241ad256  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

Update the ti-dm firmware to 08.06.01 for Jacinto devices.

These were generated using SYSFW v08.06.01

J784S4
DRU4-7 LPSC has proper MSMC LPSC dependency

d7614964f549fc120d382af8b33d07e2  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
1aad382af55064233df8c15c8e1c90d5  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
a08f479fd500fea95408ff4dacd2ca9e  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
51c5d8f8ed92d55f4fbdb1569ee5f7ea  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Sheng Zhao <shengzhao@ti.com>

Update the following ti-dm firmware
- 08.06.00.04 for am62x (MCU+)
- 08.06.03.05 for am62ax (PDK)

Major changes compared to previous version:
- AM62x: LPM stability fix

MD5 Checksum:
675b9f2dd9b2e145f685ff18e0585b66  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
e4412d73fdeb399400124ee3b5acb7a9  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware 08.06.03.04 for am62ax

Major changes compared to previous version:
- Traces added for RM PSIL host ID check
- ctrl_mmr operations fixed to not do unconditional unlocks

MD5 Checksum:
bdee3c2e0bbee458baa0ff2ef388687e  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware
08.06.00.01 for am62x

Major changes compared to previous version:
- Firmwares built out of MCU+ SDK codebase
- Traces added for RM PSIL host ID check
- ctrl_mmr operations fixed to not do unconditional unlocks
- LPM: A53 and DSS fixes after exit from deepsleep

MD5 Checksum:
3c16e4547d46829beb79269adec51c47  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Venkatesan Krishnamoorthy <v-krishnamoorthy@ti.com>
[praneeth@ti.com: updated patch to remove am62ax binary]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Update the ti-dm firmware to 08.06.00 for Jacinto devices.

These were generated using SYSFW v08.06.00

j7200
RM board config size reduced

J721E
PG2.0 support (GP & HS)
RM board config size reduced

J721S2
RM board config size reduced
VPAC DMPAC clock frequency configuration

J784S4
keywriter support
VPAC DMPAC clock frequency configuration

General
Bare-metal in TIFS
MCU R5F demotion to non-secure mode
NAVSS MCRC overlapping interrupt index

MD5 Checksum:
a5eef2f8d5bcb58f0e6b0ecafa53d8b7  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
ec9b74f653d0b21c636f564e6140f148  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
8e624c59cfbb92dffd9fd76bc0ce9c6e  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
cfd0599585fd420bc28677c4494ec1f2  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

Vishal Mahaveer authored 2 years ago and Vignesh Raghavendra committed 2 years ago

Update the following ti-dm firmware
08.05.02.03 for am62x and am62ax

Major changes compared to previous version:
- Fix for 6 channel am62ax CSI usecase DMA failure

MD5 Checksum:
6314ec1455ebeca39bb7cb0e61c10f14  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
698464b6f18ad316cab6454d8a5a02ae  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware
08.05.02 for j721e
08.05.02 for j7200
08.05.02 for j721s2
08.05.02 for j784s4

These were generated using SYSFW v08.05.02

J721E
clk_no_hw_reinit flag enabled for GTC and MPU

J7200
clk_no_hw_reinit flag enabled for GTC and MPU

J721S2
clk_no_hw_reinit flag enabled for GTC and MPU

MD5 Checksums:
c9a5aacbb69cde4efa0ca8ec24ad71ed  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
4d9177d8e853aa017a6c21a0806b50dd  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
5ddabbfa1f2a44fbeb0a865b65c3a8ef  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
e337ae8ae9c8596e1c7e877382f05c1a  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

Update the following ti-dm firmware
08.05.02.02 for am62x and am62ax

Major changes compared to previous version:
- SCISERVER fixes for MCAL issues
- Moved to latest PDK codebase where am62x and am62ax are combined

MD5 Checksum:
aa2903495852e3f83f04e0bd43828c1d  ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f
f8fbe3be35f5e4983b532ed970dcca5b  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware
08.05.00 for j721e
08.05.00 for j7200
08.05.00 for j721s2
08.05.00 for j784s4

These were generated using SYSFW v08.05.00

J7200
New device is added for main_pll8_sel_ext_wave

J721E
New device is added for main_pll8_sel_ext_wave

J721S2
SMS TIFS to HSM Communication Enablement

J784S4
Main PLL3 vco frequency changed from 2GHz to 2.5GHz
RM boardconfig size reduced
SMS TIFS to HSM Communication Enablement

MD5 Checksums:
0abe9bcb717cee88a51cd703f3cc50e7  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
1079cfd6f0c3094921b4f84dcd1edaac  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
2e1b3f964dad6713c1a8031933e36eed  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f
e91017928d7b9b3c485e8470a2e20f25  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Chandru Dhavamani <chandru@ti.com>

Update the following ti-dm firmware
08.04.01.10 for AM62x

Major changes compared to previous version:
- Updated memory map to be backward compatible with old release

MD5 Checksum:
ec41f445671447c23841a576e0e31883  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Add DM R5 firmware for AM62Ax SoC. Initial version is based on
release 08.04.01.08.
supported TIFS FW version along with this DM is v08.04.07

MD5 checksum:
4029aab8b8d661281a475b081e122aab ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Add DM FW support for J784S4 SoC.
This is part of 08.04.05

MD5 checksum:
4c886f743d1f6daa79b650332c18996d  ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Sheng Zhao <shengzhao@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

Update the following ti-dm firmware
08.04.01.08 for AM62x

Major changes compared to previous version:
- Switched to ipc echo test application to enable A53 <-> DM R5 IPC
- Switched to latest sitara PDK baseline

MD5 Checksum:
ec872a8f6e008b42cd4ab620dd6e6df4  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Update the following ti-dm firmware
08.04.01.07 for AM62x

Major changes compared to previous version:
- Fixed a DMA regression introduced in v08.04.06 update.

MD5 Checksum:
290289a12a5251e15d70ecb4b690f7ef  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware
08.04.01.06 for AM62x

Major changes compared to previous version:
- Security Audit fixes
- am62x: SPI loopback clk mux changes (previously missing mux)
- Fix bug related to wake reason message

MD5 Checksum:
e356429a275b8b9534b10fcae36b191a ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware
08.04.01.05 for AM62x

Major changes compared to previous version:
- DM trace configuration is now runtime based on TIFS boardcfg
- Add virtual device option to choose second level MCU obsclk mux option
- Fix for A53 clocks returning get freq value as 0
- Add tisci message for LPM wake reason
- Add tisci message to enable/disable IO isolation

MD5 Checksum:
881b541e9ba3bb6c2a2f9480c2c062a7  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

08.04.01.02 for AM62x

Major changes compared to previous version:
- ctrl_mmr locks to be left unlocked by DM firmware
- Software reset sequence updated to use correct ctrl_mmr registers
- ARM PLL not re-initialized by DM firmware to preserve SPL settings

MD5 Checksum:
5a4d01e4742133afd50765ae2fed2238  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>

Update the following ti-dm firmware
08.04.00.06 for j721e
08.04.00.06 for j7200
08.04.00.06 for j721s2

These were generated using SYSFW v08.04.01
J721E
PVU support enabled

J721S2
Introduction of HS-SE support, HSM boot support

General
SA2UL/SA3UL TRNG firewall open at boot on HS devices
(shared TIFS instances only)

MD5 Checksums:
239a55b0fe3d5591568b3850066e85bb  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
6669d3fae62a4ec932cb3b0d91df5252  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
2a2dfc437acc984ec66f09d9dc6bac6e  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>

Update the following dm firmware for jacinto devices.

08.04.00.05 for j721e
08.04.00.05 for j7200
08.04.00.03 for j721s2

Updated for SYSFW v08.04.00

MD5 Checksums:
5b1e461a61c8e6166cfa561a9ec274c7  ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f
a1d82d5821fdd7d6385bf9d3f0657328  ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f
a781a56a170384b54ec943b0ef9afe7b  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>

Update the following ti-dm firmware
08.00.04.11 for j721s2

Updated for SYSFW v2022.01a

MD5 Checksums:
d4210d9209f42a3b52eaffae8d268ade  ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Aditya Wadhwa <a-wadhwa@ti.com>

Update the following ti-dm firmware
08.03.00.08 for AM62x

Major changes compared to previous version:
- Fix for PSIL pairing request failure observed with Ethernet boot
- Fix for setting clk_div load bit for UART clock dividers
- Use main ctrl_mmr for software reset instead of wkup ctrl_mmr
- Trace version updated from 3.5 to 3.6 for decoding LPM messages

MD5 Checksum:
04041de1dde94c03197764e706c4055c  ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f

Signed-off-by: Vishal Mahaveer <vishalm@ti.com>