- Aug 30, 2022
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Vauban authored
- Add missing cape signals. - Adjust M.2 and base design pin constraints to match new cape pin assignments - Move immutable cape signasl pin constraints to base design's pin constraints file.
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- Aug 29, 2022
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Vauban authored
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Vauban authored
- Remove PCM signals - Reduce PCIe from 2 to 1 lane.
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Vauban authored
Let I/O pads propagate to the top level of the design and rename as required.
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Vauban authored
Couple the pin constraint files with the variant of design blocks. This should allow us to customize cape I/Os to best suit a specific cape. It also allows to easily include or excluse a block from the design. For example, not include cape, M.2, MIPI-CSI or high speed interface if not required and tight on FPGA resources.
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Vauban authored
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- Jun 12, 2022
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Vauban authored
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- Jun 10, 2022
- Jun 08, 2022
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Vauban authored
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- Jun 06, 2022
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Vauban authored
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- Jun 04, 2022
- May 29, 2022
- May 27, 2022
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Vauban authored
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- May 08, 2022
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Vauban authored
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- Apr 18, 2022
- Mar 25, 2022
- Mar 13, 2022
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Vauban authored
- Temporary removal of MIPI-CSI interface.
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- Mar 08, 2022
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Vauban authored
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- Mar 07, 2022
- Mar 06, 2022
- Mar 05, 2022
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Vauban authored
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- Feb 27, 2022
- Feb 21, 2022
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Vauban authored
- Connect Ethernet management interface to PHY. - Connect PHY reset input to FPGA system reset. - Connect PHY interrupt to MSS F2M fabric interrupt 2.
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- Feb 20, 2022
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Vauban authored
- Removed pins reserved for probe from project options to free up pin C14 and C15 for use as cape pins. - Set pin migrations to all available devices in project settins to allow migration to all devices in same package.
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Vauban authored
- Connected MMUART_4 to cape P9 connector pins 11 and 13. - Added pin constraints for cape P9 connector pins 11 and 13.
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- Feb 18, 2022
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Vauban authored
- Marked pins not available in the MPFS025-FCVG484 package. - Identified available pins not currently used in the design. - Identified pins used in the design that need to be properly document (marked as GPIO?).
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- Feb 14, 2022
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Vauban authored
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- Feb 13, 2022
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Vauban authored
- Move PCIe and closely associated block out of top level design into a new sublock containing all FPGA fabric components related to the M.2 interface.
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- Feb 12, 2022
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Vauban authored
- Connect MMUART_0 to the debug header. - Remove the second Ethernet MAC to free up pins for MMUART_0 - Connect MMUART_1 to the M.2 interface. Chose MMUART1 because RTX/CTS is avaialble on that UART.
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- Feb 11, 2022
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Vauban authored
Comment out pins from original design which are not available on FCVG484_Eval package of the MPFS025 die.
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