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Commit fec40fdd authored by Vauban's avatar Vauban
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Design structure: split "constant" RISC-V subsystem from FPGA design.

parent a31160a7
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......@@ -33,5 +33,6 @@ source script_support/components/CAPE_DEFAULT_GPIOS.tcl
source script_support/components/CAPE_PWM.tcl
source script_support/components/CAPE.tcl
source script_support/components/M2_INTERFACE.tcl
source script_support/components/BVF_RISCV_SUBSYSTEM.tcl
source script_support/components/B_V_F_BASE_DESIGN.tcl
set_root -module {B_V_F_BASE_DESIGN::work}
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......@@ -4,12 +4,12 @@
# Create and Configure the core component FIC3_INITIATOR
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {FIC3_INITIATOR} -params {\
"APB_DWIDTH:32" \
"APBSLOT0ENABLE:false" \
"APBSLOT0ENABLE:true" \
"APBSLOT1ENABLE:true" \
"APBSLOT2ENABLE:true" \
"APBSLOT3ENABLE:false" \
"APBSLOT4ENABLE:true" \
"APBSLOT5ENABLE:true" \
"APBSLOT3ENABLE:true" \
"APBSLOT4ENABLE:false" \
"APBSLOT5ENABLE:false" \
"APBSLOT6ENABLE:false" \
"APBSLOT7ENABLE:false" \
"APBSLOT8ENABLE:false" \
......@@ -19,18 +19,18 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -compon
"APBSLOT12ENABLE:false" \
"APBSLOT13ENABLE:false" \
"APBSLOT14ENABLE:false" \
"APBSLOT15ENABLE:true" \
"APBSLOT15ENABLE:false" \
"IADDR_OPTION:0" \
"MADDR_BITS:28" \
"SC_0:false" \
"SC_1:false" \
"SC_2:false" \
"SC_3:true" \
"SC_3:false" \
"SC_4:false" \
"SC_5:false" \
"SC_6:false" \
"SC_7:false" \
"SC_8:true" \
"SC_8:false" \
"SC_9:false" \
"SC_10:false" \
"SC_11:false" \
......
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