Design structure: Add option to omit the cape logic and IOs from the design.

B_V_F_REFERENCE_DESIGN.tcl

@@ -54,6 +54,13 @@ set local_dir [pwd]
 set constraint_path ./script_support/constraints
 set project_name "B_V_F_025"
 
+if {[info exists CAPE_OPTION]} {
+    set cape_option "$CAPE_OPTION"
+} else {
+    set cape_option "DEFAULT"
+}
+
+
 if {[info exists PROJECT_LOCATION]} {
     set project_dir "$PROJECT_LOCATION"
 } else {
@@ -136,7 +143,6 @@ source ./script_support/B_V_F_recursive.tcl
 import_files \
     -convert_EDN_to_HDL 0 \
     -io_pdc "${constraint_path}/base_design.pdc" \
-    -io_pdc "${constraint_path}/cape.pdc" \
     -io_pdc "${constraint_path}/M2.pdc" \
     -io_pdc "${constraint_path}/M2_USB.pdc" \
     -io_pdc "${constraint_path}/ICICLE_USB.pdc"
@@ -148,13 +154,30 @@ import_files \
 organize_tool_files \
     -tool {PLACEROUTE} \
     -file "${project_dir}/constraint/io/base_design.pdc" \
-    -file "${project_dir}/constraint/io/cape.pdc" \
     -file "${project_dir}/constraint/io/M2.pdc" \
     -file "${project_dir}/constraint/io/M2_USB.pdc" \
     -file "${project_dir}/constraint/io/ICICLE_USB.pdc" \
     -module {B_V_F_BASE_DESIGN::work} \
     -input_type {constraint}
 
+#
+# Add relevant cape related constraints.
+#
+if {$cape_option == "DEFAULT"} {
+
+    import_files \
+        -convert_EDN_to_HDL 0 \
+        -io_pdc "${constraint_path}/cape.pdc"
+
+    organize_tool_files \
+        -tool {PLACEROUTE} \
+        -file "${project_dir}/constraint/io/cape.pdc" \
+        -module {B_V_F_BASE_DESIGN::work} \
+        -input_type {constraint}
+
+}
+
+
 #
 # // Derive timing constraints
 #

script_support/B_V_F_recursive.tcl

@@ -28,11 +28,11 @@ source script_support/components/CLOCKS_AND_RESETS/CLOCKS_AND_RESETS.tcl
 source script_support/components/CLOCKS_AND_RESETS/ADD_PCIE_CLOCKS_AND_RESETS.tcl 
 source script_support/components/IHC_APB.tcl
 source script_support/components/IHC_SUBSYSTEM.tcl
-source script_support/components/APB_BUS_CONVERTER.tcl
-source script_support/components/P8_GPIO_LCD.tcl
-source script_support/components/CAPE_DEFAULT_GPIOS.tcl
-source script_support/components/CAPE_PWM.tcl
-source script_support/components/CAPE.tcl
+source script_support/components/CAPE/DEFAULT/APB_BUS_CONVERTER.tcl
+source script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+source script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
+source script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
+source script_support/components/CAPE/DEFAULT/CAPE.tcl
 source script_support/components/M2_INTERFACE.tcl
 source script_support/components/BVF_RISCV_SUBSYSTEM.tcl
 source script_support/components/B_V_F_BASE_DESIGN.tcl 

script_support/components/B_V_F_BASE_DESIGN.tcl

@@ -278,8 +278,8 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:CSI_APB_
 
 #-------------------------------------------------------------------------------
 
-source script_support/components//ADD_CAPE.tcl 
-source script_support/components//ADD_M2_INTERFACE.tcl 
+source script_support/components/CAPE/$cape_option/ADD_CAPE.tcl 
+source script_support/components/ADD_M2_INTERFACE.tcl 
 
 
 #-------------------------------------------------------------------------------