Clean-up: Remove no longer required TCL scripts.

script_support/additional_configurations/DRI_CCC_DEMO/DRI_CCC_DEMO.tcl

-set sd_name {CLOCKS_AND_RESETS}
-open_smartdesign -sd_name ${sd_name}
-
-sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_100MHz} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_75MHz} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_50MHz} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_25MHz} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_CLK_0} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_ARST_N_0} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_INTERRUPT_0} -port_direction {OUT}
-
-sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_CTRL_0} -port_direction {IN} -port_range {[10:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_RDATA_0} -port_direction {OUT} -port_range {[32:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_WDATA_0} -port_direction {IN} -port_range {[32:0]}
-
-sd_create_bif_port -sd_name ${sd_name} -port_name {PLL0_DRI} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
-"DRI_CLK:DRI_CLK_0" \
-"DRI_ARST_N:DRI_ARST_N_0" \
-"DRI_CTRL:DRI_CTRL_0" \
-"DRI_RDATA:DRI_RDATA_0" \
-"DRI_WDATA:DRI_WDATA_0" \
-"DRI_INTERRUPT:DRI_INTERRUPT_0" } 
-
-
-# Add CCC instance
-sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {CCC}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_100MHz" "CCC:OUT0_FABCLK_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_75MHz" "CCC:OUT1_FABCLK_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_50MHz" "CCC:OUT2_FABCLK_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_25MHz" "CCC:OUT3_FABCLK_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"RESET_CLK_62_5MHz:PLL_POWERDOWN_B" "CCC:PLL_POWERDOWN_N_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"OSCILLATOR_160MHz:RCOSC_160MHZ_GL" "CCC:REF_CLK_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PLL0_DRI" "CCC:PLL0_DRI" }
-
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CCC:PLL_LOCK_0}
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CLOCKS_AND_RESETS
-generate_component -component_name ${sd_name}
-
-set sd_name {MPFS_ICICLE_KIT_BASE_DESIGN}
-open_smartdesign -sd_name ${sd_name}
-sd_update_instance -sd_name ${sd_name} -instance_name {CLOCKS_AND_RESETS} 
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:PLL0_DRI" "RECONFIGURATION_INTERFACE_0:PLL0_SW_DRI" }
-
-sd_disconnect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"GPIO_2_2_IO:D"} 
-sd_disconnect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"GPIO_2_2_IO:E"} 
-sd_connect_pins_to_constant -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {GPIO_2_2_IO:E} -value {VCC} 
-sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_100MHz" "GPIO_2_2_IO:D"} 
-
-sd_disconnect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"GPIO_2_4_IO:D"} 
-sd_disconnect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"GPIO_2_4_IO:E"} 
-sd_connect_pins_to_constant -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {GPIO_2_4_IO:E} -value {VCC} 
-sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_75MHz" "GPIO_2_4_IO:D"} 
-
-sd_disconnect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"GPIO_2_8_IO:D"} 
-sd_disconnect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"GPIO_2_8_IO:E"} 
-sd_connect_pins_to_constant -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {GPIO_2_8_IO:E} -value {VCC} 
-sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_50MHz" "GPIO_2_8_IO:D"} 
-
-sd_disconnect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"GPIO_2_9_IO:D"} 
-sd_disconnect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"GPIO_2_9_IO:E"} 
-sd_connect_pins_to_constant -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {GPIO_2_9_IO:E} -value {VCC} 
-sd_connect_pins -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -pin_names {"CLOCKS_AND_RESETS:CLK_25MHz" "GPIO_2_9_IO:D"} 
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CLOCKS_AND_RESETS
-generate_component -component_name ${sd_name}
-
-import_files -convert_EDN_to_HDL 0 -fp_pdc "${constraint_path}/CCC.pdc"
-
-organize_tool_files \
-    -tool {PLACEROUTE} \
-    -file "${project_dir}/constraint/fp/CCC.pdc" \
-    -module {MPFS_ICICLE_KIT_BASE_DESIGN::work} \
-    -input_type {constraint}
-
-build_design_hierarchy
-derive_constraints_sdc 

script_support/additional_configurations/I2C_LOOPBACK/I2C_LOOPBACK.tcl

-set sd_name {MPFS_ICICLE_KIT_BASE_DESIGN}
-open_smartdesign -sd_name ${sd_name}
-delete_component -component_name {ICICLE_MSS} 
-import_mss_component -file "$local_dir/script_support/components/MSS_I2C_LOOPBACK/ICICLE_MSS.cxz"
-sd_update_instance -sd_name ${sd_name} -instance_name {ICICLE_MSS} 
-
-# Add I2C1_SCL_BIBUF instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {I2C1_SCL_BIBUF}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {I2C1_SCL_BIBUF:D} -value {GND}
-
-# Add I2C1_SDA_BIBUF instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {I2C1_SDA_BIBUF}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {I2C1_SDA_BIBUF:D} -value {GND}
-
-sd_rename_port -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -current_port_name {PAD} -new_port_name {I2C1_SCL} 
-sd_rename_port -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -current_port_name {PAD_0} -new_port_name {I2C1_SDA} 
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"ICICLE_MSS:I2C_1_SCL_F2M" "I2C1_SCL_BIBUF:Y" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"ICICLE_MSS:I2C_1_SDA_F2M" "I2C1_SDA_BIBUF:Y" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"ICICLE_MSS:I2C_1_SCL_OE_M2F" "I2C1_SCL_BIBUF:E" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"ICICLE_MSS:I2C_1_SDA_OE_M2F" "I2C1_SDA_BIBUF:E" }
-
-generate_component -component_name ${sd_name} -recursive 0 
-build_design_hierarchy
-
-organize_tool_files -tool {PLACEROUTE} -file "${project_dir}/constraint/io/ICICLE_CAN0.pdc" -file "${project_dir}/constraint/io/ICICLE_SDIO.pdc" -file "${project_dir}/constraint/io/ICICLE_USB.pdc" -file "${project_dir}/constraint/io/ICICLE.pdc" -file "${project_dir}/constraint/io/ICICLE_MAC.pdc" -file "${project_dir}/constraint/io/ICICLE_PCIE.pdc" -file "${project_dir}/constraint/io/ICICLE_MMUART0.pdc" -file "${project_dir}/constraint/io/ICICLE_MMUART1.pdc" -file "${project_dir}/constraint/io/ICICLE_MMUART3.pdc" -file "${project_dir}/constraint/io/ICICLE_MMUART2.pdc" -file "${project_dir}/constraint/io/ICICLE_I2C_LOOPBACK.pdc" -module {MPFS_ICICLE_KIT_BASE_DESIGN::work} -input_type {constraint} 

script_support/additional_configurations/SPI_LOOPBACK/SPI_LOOPBACK.tcl

-set sd_name {MPFS_ICICLE_KIT_BASE_DESIGN}
-open_smartdesign -sd_name ${sd_name}
-delete_component -component_name {ICICLE_MSS} 
-import_mss_component -file "$local_dir/script_support/components/MSS_SPI_LOOPBACK/ICICLE_MSS.cxz"
-sd_update_instance -sd_name ${sd_name} -instance_name {ICICLE_MSS} 
-
-sd_delete_instances -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -instance_names {"QSPI_DATA2_BIBUF"} 
-sd_delete_instances -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -instance_names {"QSPI_DATA3_OR_PWM_BIBUF"} 
-sd_delete_instances -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -instance_names {"QSPI_DATA3_OR_PWM_D_OR"} 
-sd_delete_instances -sd_name {MPFS_ICICLE_KIT_BASE_DESIGN} -instance_names {"QSPI_DATA3_OR_PWM_EN_OR"} 
-
-generate_component -component_name {MPFS_ICICLE_KIT_BASE_DESIGN} -recursive 0 
-
-generate_component -component_name ${sd_name} -recursive 0 
-build_design_hierarchy
-
-organize_tool_files -tool {PLACEROUTE} -file "${project_dir}/constraint/io/ICICLE_CAN0.pdc" -file "${project_dir}/constraint/io/ICICLE_SDIO.pdc" -file "${project_dir}/constraint/io/ICICLE_USB.pdc" -file "${project_dir}/constraint/io/ICICLE.pdc" -file "${project_dir}/constraint/io/ICICLE_MAC.pdc" -file "${project_dir}/constraint/io/ICICLE_PCIE.pdc" -file "${project_dir}/constraint/io/ICICLE_MMUART0.pdc" -file "${project_dir}/constraint/io/ICICLE_MMUART1.pdc" -file "${project_dir}/constraint/io/ICICLE_MMUART3.pdc" -file "${project_dir}/constraint/io/ICICLE_MMUART2.pdc" -file "${project_dir}/constraint/io/ICICLE_SPI_LOOPBACK.pdc" -module {MPFS_ICICLE_KIT_BASE_DESIGN::work} -input_type {constraint} 

script_support/additional_configurations/Vectorblox/Vectorblox_ss_recursive.tcl

-#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion
-
-#Sourcing the Tcl files for creating individual components under the top level
-source components/CORERESET_PF_C0.tcl 
-source components/core_vectorblox_C0.tcl 
-source components/PF_CCC_C1.tcl 
-source components/vectorblox_axi_resize.tcl 
-source components/Vectorblox_ss.tcl 
-build_design_hierarchy

script_support/additional_configurations/Vectorblox/components/CORERESET_PF_C0.tcl

-# Exporting Component Description of CORERESET_PF_C0 to TCL
-# Family: PolarFireSoC
-# Part Number: MPFS250T_ES-FCVG484E
-# Create and Configure the core component CORERESET_PF_C0
-create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C0} -params { }
-# Exporting Component Description of CORERESET_PF_C0 to TCL done

script_support/additional_configurations/Vectorblox/components/PF_CCC_C1.tcl

-# Exporting Component Description of PF_CCC_C1 to TCL
-# Family: PolarFireSoC
-# Part Number: MPFS250T_ES-FCVG484E
-# Create and Configure the core component PF_CCC_C1
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.100} -component_name {PF_CCC_C1} -params {\
-"DLL_CLK_0_BANKCLK_EN:false"  \
-"DLL_CLK_0_DEDICATED_EN:false"  \
-"DLL_CLK_0_FABCLK_EN:false"  \
-"DLL_CLK_1_BANKCLK_EN:false"  \
-"DLL_CLK_1_DEDICATED_EN:false"  \
-"DLL_CLK_1_FABCLK_EN:false"  \
-"DLL_CLK_P_EN:false"  \
-"DLL_CLK_P_OPTIONS_EN:false"  \
-"DLL_CLK_REF_OPTION:DIVIDE_BY_1"  \
-"DLL_CLK_REF_OPTIONS_EN:false"  \
-"DLL_CLK_S_EN:false"  \
-"DLL_CLK_S_OPTION:DIVIDE_BY_1"  \
-"DLL_CLK_S_OPTIONS_EN:false"  \
-"DLL_DELAY4:0"  \
-"DLL_DYNAMIC_CODE_EN:false"  \
-"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false"  \
-"DLL_EXPORT_PWRDWN:true"  \
-"DLL_FB_CLK:Primary"  \
-"DLL_FB_EN:false"  \
-"DLL_FINE_PHASE_CODE:0"  \
-"DLL_IN:133"  \
-"DLL_JITTER:0"  \
-"DLL_MODE:PHASE_REF_MODE"  \
-"DLL_ONLY_EN:false"  \
-"DLL_OUT_0:1"  \
-"DLL_OUT_1:1"  \
-"DLL_PRIM_PHASE:90"  \
-"DLL_PRIM_PHASE_CODE:0"  \
-"DLL_SEC_PHASE:90"  \
-"DLL_SEC_PHASE_CODE:0"  \
-"DLL_SELECTED_IN:Output2"  \
-"FF_REQUIRES_LOCK_EN_0:0"  \
-"GL0_0_BANKCLK_USED:false"  \
-"GL0_0_BYPASS:0"  \
-"GL0_0_BYPASS_EN:false"  \
-"GL0_0_DEDICATED_USED:false"  \
-"GL0_0_DIV:12"  \
-"GL0_0_DIVSTART:0"  \
-"GL0_0_DYNAMIC_PH:false"  \
-"GL0_0_EXPOSE_EN:false"  \
-"GL0_0_FABCLK_GATED_USED:false"  \
-"GL0_0_FABCLK_USED:true"  \
-"GL0_0_FREQ_SEL:false"  \
-"GL0_0_IS_USED:true"  \
-"GL0_0_OUT_FREQ:100"  \
-"GL0_0_PHASE_INDEX:0"  \
-"GL0_0_PHASE_SEL:false"  \
-"GL0_0_PLL_PHASE:0"  \
-"GL0_1_BANKCLK_USED:false"  \
-"GL0_1_BYPASS:0"  \
-"GL0_1_BYPASS_EN:false"  \
-"GL0_1_DEDICATED_USED:false"  \
-"GL0_1_DIV:1"  \
-"GL0_1_DIVSTART:0"  \
-"GL0_1_DYNAMIC_PH:false"  \
-"GL0_1_EXPOSE_EN:false"  \
-"GL0_1_FABCLK_USED:false"  \
-"GL0_1_FREQ_SEL:false"  \
-"GL0_1_IS_USED:true"  \
-"GL0_1_OUT_FREQ:100"  \
-"GL0_1_PHASE_INDEX:0"  \
-"GL0_1_PHASE_SEL:false"  \
-"GL0_1_PLL_PHASE:0"  \
-"GL1_0_BANKCLK_USED:false"  \
-"GL1_0_BYPASS:0"  \
-"GL1_0_BYPASS_EN:false"  \
-"GL1_0_DEDICATED_USED:false"  \
-"GL1_0_DIV:6"  \
-"GL1_0_DIVSTART:0"  \
-"GL1_0_DYNAMIC_PH:false"  \
-"GL1_0_EXPOSE_EN:false"  \
-"GL1_0_FABCLK_GATED_USED:false"  \
-"GL1_0_FABCLK_USED:true"  \
-"GL1_0_FREQ_SEL:false"  \
-"GL1_0_IS_USED:true"  \
-"GL1_0_OUT_FREQ:200"  \
-"GL1_0_PHASE_INDEX:0"  \
-"GL1_0_PHASE_SEL:false"  \
-"GL1_0_PLL_PHASE:0"  \
-"GL1_1_BANKCLK_USED:false"  \
-"GL1_1_BYPASS:0"  \
-"GL1_1_BYPASS_EN:false"  \
-"GL1_1_DEDICATED_USED:false"  \
-"GL1_1_DIV:1"  \
-"GL1_1_DIVSTART:0"  \
-"GL1_1_DYNAMIC_PH:false"  \
-"GL1_1_EXPOSE_EN:false"  \
-"GL1_1_FABCLK_USED:false"  \
-"GL1_1_FREQ_SEL:false"  \
-"GL1_1_IS_USED:false"  \
-"GL1_1_OUT_FREQ:0"  \
-"GL1_1_PHASE_INDEX:0"  \
-"GL1_1_PHASE_SEL:false"  \
-"GL1_1_PLL_PHASE:0"  \
-"GL2_0_BANKCLK_USED:false"  \
-"GL2_0_BYPASS:0"  \
-"GL2_0_BYPASS_EN:false"  \
-"GL2_0_DEDICATED_USED:false"  \
-"GL2_0_DIV:1"  \
-"GL2_0_DIVSTART:0"  \
-"GL2_0_DYNAMIC_PH:false"  \
-"GL2_0_EXPOSE_EN:false"  \
-"GL2_0_FABCLK_GATED_USED:false"  \
-"GL2_0_FABCLK_USED:true"  \
-"GL2_0_FREQ_SEL:false"  \
-"GL2_0_IS_USED:false"  \
-"GL2_0_OUT_FREQ:100"  \
-"GL2_0_PHASE_INDEX:0"  \
-"GL2_0_PHASE_SEL:false"  \
-"GL2_0_PLL_PHASE:0"  \
-"GL2_1_BANKCLK_USED:false"  \
-"GL2_1_BYPASS:0"  \
-"GL2_1_BYPASS_EN:false"  \
-"GL2_1_DEDICATED_USED:false"  \
-"GL2_1_DIV:1"  \
-"GL2_1_DIVSTART:0"  \
-"GL2_1_DYNAMIC_PH:false"  \
-"GL2_1_EXPOSE_EN:false"  \
-"GL2_1_FABCLK_USED:false"  \
-"GL2_1_FREQ_SEL:false"  \
-"GL2_1_IS_USED:false"  \
-"GL2_1_OUT_FREQ:0"  \
-"GL2_1_PHASE_INDEX:0"  \
-"GL2_1_PHASE_SEL:false"  \
-"GL2_1_PLL_PHASE:0"  \
-"GL3_0_BANKCLK_USED:false"  \
-"GL3_0_BYPASS:0"  \
-"GL3_0_BYPASS_EN:false"  \
-"GL3_0_DEDICATED_USED:false"  \
-"GL3_0_DIV:1"  \
-"GL3_0_DIVSTART:0"  \
-"GL3_0_DYNAMIC_PH:false"  \
-"GL3_0_EXPOSE_EN:false"  \
-"GL3_0_FABCLK_GATED_USED:false"  \
-"GL3_0_FABCLK_USED:true"  \
-"GL3_0_FREQ_SEL:false"  \
-"GL3_0_IS_USED:false"  \
-"GL3_0_OUT_FREQ:100"  \
-"GL3_0_PHASE_INDEX:0"  \
-"GL3_0_PHASE_SEL:false"  \
-"GL3_0_PLL_PHASE:0"  \
-"GL3_1_BANKCLK_USED:false"  \
-"GL3_1_BYPASS:0"  \
-"GL3_1_BYPASS_EN:false"  \
-"GL3_1_DEDICATED_USED:false"  \
-"GL3_1_DIV:1"  \
-"GL3_1_DIVSTART:0"  \
-"GL3_1_DYNAMIC_PH:false"  \
-"GL3_1_EXPOSE_EN:false"  \
-"GL3_1_FABCLK_USED:false"  \
-"GL3_1_FREQ_SEL:false"  \
-"GL3_1_IS_USED:false"  \
-"GL3_1_OUT_FREQ:0"  \
-"GL3_1_PHASE_INDEX:0"  \
-"GL3_1_PHASE_SEL:false"  \
-"GL3_1_PLL_PHASE:0"  \
-"PLL_ALLOW_CCC_EXT_FB:false"  \
-"PLL_BANDWIDTH_0:2"  \
-"PLL_BANDWIDTH_1:1"  \
-"PLL_BYPASS_GO_B_0:false"  \
-"PLL_BYPASS_GO_B_1:false"  \
-"PLL_BYPASS_POST_0:0"  \
-"PLL_BYPASS_POST_0_0:false"  \
-"PLL_BYPASS_POST_0_1:false"  \
-"PLL_BYPASS_POST_0_2:false"  \
-"PLL_BYPASS_POST_0_3:false"  \
-"PLL_BYPASS_POST_1:0"  \
-"PLL_BYPASS_POST_1_0:false"  \
-"PLL_BYPASS_POST_1_1:false"  \
-"PLL_BYPASS_POST_1_2:false"  \
-"PLL_BYPASS_POST_1_3:false"  \
-"PLL_BYPASS_PRE_0:0"  \
-"PLL_BYPASS_PRE_0_0:false"  \
-"PLL_BYPASS_PRE_0_1:false"  \
-"PLL_BYPASS_PRE_0_2:false"  \
-"PLL_BYPASS_PRE_0_3:false"  \
-"PLL_BYPASS_PRE_1:0"  \
-"PLL_BYPASS_PRE_1_0:false"  \
-"PLL_BYPASS_PRE_1_1:false"  \
-"PLL_BYPASS_PRE_1_2:false"  \
-"PLL_BYPASS_PRE_1_3:false"  \
-"PLL_BYPASS_SEL_0:0"  \
-"PLL_BYPASS_SEL_0_0:false"  \
-"PLL_BYPASS_SEL_0_1:false"  \
-"PLL_BYPASS_SEL_0_2:false"  \
-"PLL_BYPASS_SEL_0_3:false"  \
-"PLL_BYPASS_SEL_1:0"  \
-"PLL_BYPASS_SEL_1_0:false"  \
-"PLL_BYPASS_SEL_1_1:false"  \
-"PLL_BYPASS_SEL_1_2:false"  \
-"PLL_BYPASS_SEL_1_3:false"  \
-"PLL_DELAY_LINE_REF_FB_0:false"  \
-"PLL_DELAY_LINE_REF_FB_1:false"  \
-"PLL_DELAY_LINE_USED_0:false"  \
-"PLL_DELAY_LINE_USED_1:false"  \
-"PLL_DELAY_STEPS_0:1"  \
-"PLL_DELAY_STEPS_1:1"  \
-"PLL_DLL_CASCADED_EN:false"  \
-"PLL_DYNAMIC_CONTROL_EN_0:true"  \
-"PLL_DYNAMIC_CONTROL_EN_1:false"  \
-"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false"  \
-"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false"  \
-"PLL_EXPORT_PWRDWN:false"  \
-"PLL_EXT_MAX_ADDR_0:128"  \
-"PLL_EXT_MAX_ADDR_1:128"  \
-"PLL_EXT_WAVE_SEL_0:0"  \
-"PLL_EXT_WAVE_SEL_1:0"  \
-"PLL_FB_CLK_0:GL0_0"  \
-"PLL_FB_CLK_1:GL0_1"  \
-"PLL_FEEDBACK_MODE_0:Post-VCO"  \
-"PLL_FEEDBACK_MODE_1:Post-VCO"  \
-"PLL_IN_FREQ_0:160"  \
-"PLL_IN_FREQ_1:100"  \
-"PLL_INT_MODE_EN_0:false"  \
-"PLL_INT_MODE_EN_1:false"  \
-"PLL_LOCK_COUNT_0:0"  \
-"PLL_LOCK_COUNT_1:0"  \
-"PLL_LP_REQUIRES_LOCK_EN_0:false"  \
-"PLL_LP_REQUIRES_LOCK_EN_1:false"  \
-"PLL_PLL_CASCADED_EN:false"  \
-"PLL_PLL_CASCADED_SELECTED_CLK:Output2"  \
-"PLL_POSTDIVIDERADDSOFTLOGIC_0:true"  \
-"PLL_REF_CLK_SEL_0:false"  \
-"PLL_REF_CLK_SEL_1:false"  \
-"PLL_REFDIV_0:5"  \
-"PLL_REFDIV_1:1"  \
-"PLL_SPREAD_MODE_0:false"  \
-"PLL_SPREAD_MODE_1:false"  \
-"PLL_SSM_DEPTH_0:5"  \
-"PLL_SSM_DEPTH_1:5"  \
-"PLL_SSM_DIVVAL_0:1"  \
-"PLL_SSM_DIVVAL_1:1"  \
-"PLL_SSM_FREQ_0:32"  \
-"PLL_SSM_FREQ_1:32"  \
-"PLL_SSM_RAND_PATTERN_0:2"  \
-"PLL_SSM_RAND_PATTERN_1:2"  \
-"PLL_SSMD_EN_0:false"  \
-"PLL_SSMD_EN_1:false"  \
-"PLL_SYNC_CORNER_PLL:false"  \
-"PLL_SYNC_EN:false"  \
-"PLL_VCO_MODE_0:MIN_JITTER"  \
-"PLL_VCO_MODE_1:MIN_JITTER"   }
-# Exporting Component Description of PF_CCC_C1 to TCL done

script_support/additional_configurations/Vectorblox/components/Vectorblox_ss.tcl

-# Creating SmartDesign Vectorblox_ss
-set sd_name {Vectorblox_ss}
-create_smartdesign -sd_name ${sd_name}
-
-# Disable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 0
-
-# Create top level Ports
-sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_0} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {aclk} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {aclk_control} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_awvalid} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_awready} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_wvalid} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_wready} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_bvalid} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_bready} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_arvalid} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_arready} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_rvalid} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {s_axi_rready} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_AWVALID} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_AWREADY} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_WLAST} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_WVALID} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_WREADY} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_BVALID} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_BREADY} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_ARVALID} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_ARREADY} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_RLAST} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_RVALID} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_RREADY} -port_direction {OUT}
-
-sd_create_bus_port -sd_name ${sd_name} -port_name {s_axi_awaddr} -port_direction {IN} -port_range {[11:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {s_axi_wdata} -port_direction {IN} -port_range {[31:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {s_axi_wstrb} -port_direction {IN} -port_range {[3:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {s_axi_bresp} -port_direction {OUT} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {s_axi_araddr} -port_direction {IN} -port_range {[11:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {s_axi_rdata} -port_direction {OUT} -port_range {[31:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {s_axi_rresp} -port_direction {OUT} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWID} -port_direction {OUT} -port_range {[8:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWADDR} -port_direction {OUT} -port_range {[37:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWLEN} -port_direction {OUT} -port_range {[7:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWBURST} -port_direction {OUT} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWPROT} -port_direction {OUT} -port_range {[2:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWQOS} -port_direction {OUT} -port_range {[3:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWREGION} -port_direction {OUT} -port_range {[3:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_WDATA} -port_direction {OUT} -port_range {[63:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_WSTRB} -port_direction {OUT} -port_range {[7:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_BID} -port_direction {IN} -port_range {[8:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_BRESP} -port_direction {IN} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARID} -port_direction {OUT} -port_range {[8:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARADDR} -port_direction {OUT} -port_range {[37:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARLEN} -port_direction {OUT} -port_range {[7:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARBURST} -port_direction {OUT} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARPROT} -port_direction {OUT} -port_range {[2:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARQOS} -port_direction {OUT} -port_range {[3:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARREGION} -port_direction {OUT} -port_range {[3:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_RID} -port_direction {IN} -port_range {[8:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_RDATA} -port_direction {IN} -port_range {[63:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_RRESP} -port_direction {IN} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWUSER} -port_direction {OUT} -port_range {[0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_WUSER} -port_direction {OUT} -port_range {[0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_BUSER} -port_direction {IN} -port_range {[0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARUSER} -port_direction {OUT} -port_range {[0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_RUSER} -port_direction {IN} -port_range {[0]}
-
-sd_create_bif_port -sd_name ${sd_name} -port_name {S_control} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
-"AWADDR:s_axi_awaddr" \
-"AWVALID:s_axi_awvalid" \
-"AWREADY:s_axi_awready" \
-"WDATA:s_axi_wdata" \
-"WSTRB:s_axi_wstrb" \
-"WVALID:s_axi_wvalid" \
-"WREADY:s_axi_wready" \
-"BRESP:s_axi_bresp" \
-"BVALID:s_axi_bvalid" \
-"BREADY:s_axi_bready" \
-"ARADDR:s_axi_araddr" \
-"ARVALID:s_axi_arvalid" \
-"ARREADY:s_axi_arready" \
-"RDATA:s_axi_rdata" \
-"RRESP:s_axi_rresp" \
-"RVALID:s_axi_rvalid" \
-"RREADY:s_axi_rready" } 
-
-sd_create_bif_port -sd_name ${sd_name} -port_name {AXIM} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
-"AWID:SLAVE0_AWID" \
-"AWADDR:SLAVE0_AWADDR" \
-"AWLEN:SLAVE0_AWLEN" \
-"AWSIZE:SLAVE0_AWSIZE" \
-"AWBURST:SLAVE0_AWBURST" \
-"AWLOCK:SLAVE0_AWLOCK" \
-"AWCACHE:SLAVE0_AWCACHE" \
-"AWPROT:SLAVE0_AWPROT" \
-"AWQOS:SLAVE0_AWQOS" \
-"AWREGION:SLAVE0_AWREGION" \
-"AWVALID:SLAVE0_AWVALID" \
-"AWREADY:SLAVE0_AWREADY" \
-"WDATA:SLAVE0_WDATA" \
-"WSTRB:SLAVE0_WSTRB" \
-"WLAST:SLAVE0_WLAST" \
-"WVALID:SLAVE0_WVALID" \
-"WREADY:SLAVE0_WREADY" \
-"BID:SLAVE0_BID" \
-"BRESP:SLAVE0_BRESP" \
-"BVALID:SLAVE0_BVALID" \
-"BREADY:SLAVE0_BREADY" \
-"ARID:SLAVE0_ARID" \
-"ARADDR:SLAVE0_ARADDR" \
-"ARLEN:SLAVE0_ARLEN" \
-"ARSIZE:SLAVE0_ARSIZE" \
-"ARBURST:SLAVE0_ARBURST" \
-"ARLOCK:SLAVE0_ARLOCK" \
-"ARCACHE:SLAVE0_ARCACHE" \
-"ARPROT:SLAVE0_ARPROT" \
-"ARQOS:SLAVE0_ARQOS" \
-"ARREGION:SLAVE0_ARREGION" \
-"ARVALID:SLAVE0_ARVALID" \
-"ARREADY:SLAVE0_ARREADY" \
-"RID:SLAVE0_RID" \
-"RDATA:SLAVE0_RDATA" \
-"RRESP:SLAVE0_RRESP" \
-"RLAST:SLAVE0_RLAST" \
-"RVALID:SLAVE0_RVALID" \
-"RREADY:SLAVE0_RREADY" \
-"AWUSER:SLAVE0_AWUSER" \
-"WUSER:SLAVE0_WUSER" \
-"BUSER:SLAVE0_BUSER" \
-"ARUSER:SLAVE0_ARUSER" \
-"RUSER:SLAVE0_RUSER" } 
-
-# Add core_vectorblox_C0_0 instance
-sd_instantiate_component -sd_name ${sd_name} -component_name {core_vectorblox_C0} -instance_name {core_vectorblox_C0_0}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {core_vectorblox_C0_0:output_valid}
-
-
-
-# Add fast_reset instance
-sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C0} -instance_name {fast_reset}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {fast_reset:BANK_x_VDDI_STATUS} -value {VCC}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {fast_reset:BANK_y_VDDI_STATUS} -value {VCC}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {fast_reset:SS_BUSY} -value {GND}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {fast_reset:FF_US_RESTORE} -value {GND}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {fast_reset:FPGA_POR_N} -value {VCC}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {fast_reset:PLL_POWERDOWN_B}
-
-
-
-# Add PF_CCC_C1_0 instance
-sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C1} -instance_name {PF_CCC_C1_0}
-
-
-
-# Add slow_reset instance
-sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C0} -instance_name {slow_reset}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {slow_reset:BANK_x_VDDI_STATUS} -value {VCC}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {slow_reset:BANK_y_VDDI_STATUS} -value {VCC}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {slow_reset:SS_BUSY} -value {GND}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {slow_reset:FF_US_RESTORE} -value {GND}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {slow_reset:FPGA_POR_N} -value {VCC}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {slow_reset:PLL_POWERDOWN_B}
-
-
-
-# Add vectorblox_axi_resize_0 instance
-sd_instantiate_component -sd_name ${sd_name} -component_name {vectorblox_axi_resize} -instance_name {vectorblox_axi_resize_0}
-
-
-
-# Add scalar net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"core_vectorblox_C0_0:clk_2x" "PF_CCC_C1_0:OUT1_FABCLK_0" "vectorblox_axi_resize_0:ACLK" "fast_reset:CLK" "aclk" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"core_vectorblox_C0_0:clk" "slow_reset:CLK" "PF_CCC_C1_0:OUT0_FABCLK_0" "vectorblox_axi_resize_0:M_CLK0" "aclk_control" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"slow_reset:EXT_RST_N" "fast_reset:EXT_RST_N" "EXT_RST_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"vectorblox_axi_resize_0:ARESETN" "fast_reset:FABRIC_RESET_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"slow_reset:INIT_DONE" "fast_reset:INIT_DONE" "INIT_DONE" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:PLL_LOCK_0" "slow_reset:PLL_LOCK" "fast_reset:PLL_LOCK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:REF_CLK_0" "REF_CLK_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"core_vectorblox_C0_0:resetn" "slow_reset:FABRIC_RESET_N" }
-
-
-# Add bus interface net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"vectorblox_axi_resize_0:AXI4mslave0" "AXIM" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"vectorblox_axi_resize_0:AXI4mmaster0" "core_vectorblox_C0_0:M_AXI" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"S_control" "core_vectorblox_C0_0:S_control" }
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign Vectorblox_ss
-generate_component -component_name ${sd_name}

script_support/additional_configurations/Vectorblox/components/core_vectorblox_C0.tcl

-# Exporting Component Description of core_vectorblox_C0 to TCL
-# Family: PolarFireSoC
-# Part Number: MPFS250T_ES-FCVG484E
-# Create and Configure the core component core_vectorblox_C0
-create_and_configure_core -core_vlnv {Microchip:SolutionCore:core_vectorblox:1.1.12} -component_name {core_vectorblox_C0} -params {\
-"M_AXI_DATA_WIDTH:128"  \
-"PRESET:2"   }
-# Exporting Component Description of core_vectorblox_C0 to TCL done

script_support/simulation/ICICLE_MSS_PFSOC_MSS_FIC0_user.bfm

-#===========================================================
-# NOTES about this specific file:
-#       In this file, 'ICICLE_MSS_PFSOC_MSS_FIC0_user.bfm', we access FIC0
-#       to perform read and write operation into LSRAM
-#===========================================================                                                                                                    
-#                                                           
-# memmap    resource_name base_address;    
-memmap FIC_0_0x61000000 0x6100_0000;                 
-#-----------------------------------------------------------
-procedure main;
-#-----------------------------------------------------------
-# START of BFM
-#-----------------------------------------------------------
-print "-"
-print "MESSAGE:  START Running BFM file 'ICICLE_MSS_PFSOC_MSS_FIC0_user.bfm'"
-print "MESSAGE:  to access FIC0"
-print "-"
-
-#-----------------------------------------------------------
-# WAIT until RESET is stable, then start BFM
-#-----------------------------------------------------------
-print "-"
-print "MESSAGE:  WAIT for some TIME after RESET released for Logic to stabilize before bus transactions"
-print "-"
-# Re-define timeout
-#    timeout default is 512 clocks
-#    timeout here is expanded to 10,000 clocks, to allow for longer wait time
-timeout 10000;
-
-#
-# WAIT until simulation time is 5us
-# 
-waitus 5;
-#
-
-#-----------------------------------------------------------
-# Perform Read and Write operation into LSRAM Meemory at address 0x6100_0000
-#-----------------------------------------------------------
-
-
-#command syntax
-#write64 x <address> <address_increment> <integer variable for MSB> <integer variable for LSB>
-#read64 x <address> <address_increment>
-
-
-#64 bit read and write command 
-print "MESSAGE:  WRITING 64 bit data to address 0x61000000"
-write64 w FIC_0_0x61000000 0x0 0x10111213 0x20212223;
-print "MESSAGE:  READING 64 bit data from address 0x61000000"
-read64 w FIC_0_0x61000000 0x0;
-
-#32 bit Write and Read command
-print "MESSAGE:  WRITING to address 0x61000008"
-write w FIC_0_0x61000000 0x8 0xecd54431;
-print "MESSAGE:  READING from address 0x61000008"
-read w FIC_0_0x61000000 0x8;
-
-#16 bit Write and Read command
-print "MESSAGE:  WRITING to address 0x6100000C"
-write h FIC_0_0x61000000 0xC 0xcd21;
-print "MESSAGE:  READING from address 0x6100000C"
-read h FIC_0_0x61000000 0xC;
-
-#8 bit Write and Read command
-print "MESSAGE:  WRITING to address 0x6100000E"
-write b FIC_0_0x61000000 0xE 0xd4;
-print "MESSAGE:  READING from address 0x6100000E"
-read b FIC_0_0x61000000 0xE;
-
-#-----------------------------------------------------------
-# END of BFM
-#-----------------------------------------------------------
-print "-"
-print "MESSAGE:  END running BFM file 'ICICLE_MSS_PFSOC_MSS_FIC0_user.bfm'"
-print "-"
-
-return

script_support/simulation/ICICLE_MSS_PFSOC_MSS_FIC3_user.bfm

-#===========================================================
-# NOTES about this specific file:
-#       In this file, 'ICICLE_MSS_PFSOC_MSS_FIC3_user.bfm', we access FIC3
-#       to toggle GPIO outputs
-#===========================================================                                                                                                    
-#                                                           
-# memmap    resource_name base_address;   
-memmap FIC_3_at_42000000    0x42000000;                 
-#-----------------------------------------------------------
-procedure main;
-#-----------------------------------------------------------
-# START of BFM
-#-----------------------------------------------------------
-print "-"
-print "MESSAGE:  START Running BFM file 'ICICLE_MSS_PFSOC_MSS_FIC3_user.bfm'"
-print "MESSAGE:  to access FIC3"
-print "-"
-
-#-----------------------------------------------------------
-# WAIT until RESET is stable, then start BFM
-#-----------------------------------------------------------
-print "-"
-print "MESSAGE:  WAIT for some TIME after RESET released for Logic to stabilize before bus transactions"
-print "-"
-# Re-define timeout
-#    timeout default is 512 clocks
-#    timeout here is expanded to 10,000 clocks, to allow for longer wait time
-timeout 10000;
-
-#
-# WAIT until simulation time is 1us
-# 
-waitus 1;
-#
-
-#-----------------------------------------------------------
-# TEST CoreGPIO
-#-----------------------------------------------------------
-# Assert CoreGPIO bit 0,1,2,and 3
-# Write to the Output register, and read back that written value
-# Reminder:  CoreGPIO is already configured in hardware(GUI) as 4 outputs bits
-#            So, we only need to write dat to the Output Register
-#------------------------------------------------------------
-print "-"
-print "MESSAGE: TESTING CoreGPIO at base address 0x4200_0000"
-print "-"
-
-
-#command systax
-#write x <address> <address_increment> <32 bit data>
-#read x <address> <address_increment>
-
-#Assert CoreGPIO bit0=1
-write w FIC_3_at_42000000 0xA0 0x00000001;
-read w FIC_3_at_42000000 0xA0;
-#Assert CoreGPIO bit1=1
-write w FIC_3_at_42000000 0xA0 0x00000002;
-read w FIC_3_at_42000000 0xA0;
-#Assert CoreGPIO bit2=1
-write w FIC_3_at_42000000 0xA0 0x00000004;
-read w FIC_3_at_42000000 0xA0;
-#Assert CoreGPIO bit3=1
-write w FIC_3_at_42000000 0xA0 0x00000008;
-read w FIC_3_at_42000000 0xA0;
-#Assert CoreGPIO bit3,2,1,0=1
-write w FIC_3_at_42000000 0xA0 0x0000000f;
-read w FIC_3_at_42000000 0xA0;
-
-#-----------------------------------------------------------
-# END of BFM
-#-----------------------------------------------------------
-print "-"
-print "MESSAGE:  END running BFM file 'ICICLE_MSS_PFSOC_MSS_FIC3_user.bfm'"
-print "-"
-
-return
-

script_support/simulation/Test_bench.tcl

-# Create SmartDesign Test Bench
-set sd_tb_name {Test_bench}
-new_testbench_file_for_design -type {SmartDesignTestBench} -name ${sd_tb_name} -SetAsActiveStimulus 1 -source {B_V_F_BASE_DESIGN} -library {work} 
-
-# Add clk gen components
-create_and_configure_core -core_vlnv {Actel:Simulation:CLK_GEN:1.0.1} -component_name {CLK_GEN_C0} -params {"CLK_PERIOD:8000" "DUTY_CYCLE:50"} 
-sd_instantiate_component -sd_name ${sd_tb_name} -component_name {CLK_GEN_C0} -instance_name {} 
-create_and_configure_core -core_vlnv {Actel:Simulation:RESET_GEN:1.0.1} -component_name {RESET_GEN_C0} -params {"DELAY:1000" "LOGIC_LEVEL:0"} 
-sd_instantiate_component -sd_name ${sd_tb_name} -component_name {RESET_GEN_C0} -instance_name {} 
-
-# Make connections
-sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"RESET_GEN_C0_0:RESET" "B_V_F_BASE_DESIGN_0:PCIE_1_PERST_N"} 
-sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"RESET_GEN_C0_0:RESET" "B_V_F_BASE_DESIGN_0:SW4"} 
-sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"CLK_GEN_C0_0:CLK" "B_V_F_BASE_DESIGN_0:REFCLK"} 
-sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"CLK_GEN_C0_0:CLK" "B_V_F_BASE_DESIGN_0:REFCLK_N"} 
-sd_invert_pins -sd_name ${sd_tb_name} -pin_names {"B_V_F_BASE_DESIGN_0:REFCLK_N"} 
-sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"B_V_F_BASE_DESIGN_0:SGMII_RX0_P" "B_V_F_BASE_DESIGN_0:SGMII_RX0_N"} 
-sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"B_V_F_BASE_DESIGN_0:SGMII_RX0_P" "B_V_F_BASE_DESIGN_0:REF_CLK_PAD_P"} 
-sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"B_V_F_BASE_DESIGN_0:SGMII_RX0_P" "B_V_F_BASE_DESIGN_0:REF_CLK_PAD_N"} 
-sd_connect_pins -sd_name ${sd_tb_name} -pin_names {"B_V_F_BASE_DESIGN_0:SGMII_RX0_P" "B_V_F_BASE_DESIGN_0:REFCLK_N"} 
-
-# Invert pins
-sd_invert_pins -sd_name ${sd_tb_name} -pin_names {"B_V_F_BASE_DESIGN_0:SGMII_RX0_N"} 
-sd_invert_pins -sd_name ${sd_tb_name} -pin_names {"B_V_F_BASE_DESIGN_0:REF_CLK_PAD_N"} 
-
-# Tie off pins
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CAN_0_RXBUS_F2M} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CAN_1_RXBUS} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_RXD0_P} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_RXD1_N} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_RXD1_P} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_RXD2_N} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_RXD2_P} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_RXD3_N} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_RXD3_P} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_RXD0_N} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_CLK} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MMUART_1_RXD_F2M} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DIR} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SW1} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_NXT} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SW3} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SW2} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MMUART_0_RXD_F2M} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MMUART_2_RXD_F2M} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SGMII_RX1_N} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MMUART_3_RXD_F2M} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SGMII_RX1_P} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:QSPI_DATA0} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:QSPI_DATA1} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:mBUS_QSPI_DATA2} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:mBUS_QSPI_DATA3_OR_PWM} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:mBUS_I2C_SCL} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:mBUS_I2C_SDA} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:mBUS_UART_RX} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SPI_0_DI_F2M} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:COREUART_RX} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:mBUS_INT} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:COREI2C_C0_SDA} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO27} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO26} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO25} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO24} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO23} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO22} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO18} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO17} -value {GND} 
-sd_connect_pins_to_constant -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:COREI2C_C0_SCL} -value {GND} 
-
-# Promote pins to top level
-sd_connect_pin_to_port -sd_name ${sd_tb_name} -pin_name {B_V_F_BASE_DESIGN_0:SDIO_SW_SEL1} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_tb_name} -pin_name {B_V_F_BASE_DESIGN_0:RPi_GPIO5} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_tb_name} -pin_name {B_V_F_BASE_DESIGN_0:RPi_GPIO6} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_tb_name} -pin_name {B_V_F_BASE_DESIGN_0:RPi_GPIO13} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_tb_name} -pin_name {B_V_F_BASE_DESIGN_0:RPi_GPIO19} -port_name {} 
-
-# Mark outputs unused
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SDIO_SW_SEL0} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CAN_1_TX_EBL_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_TXD3_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:I2C_1_SDA} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SGMII_TX1_P} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_TXD3_P} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:I2C_1_SCL} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:LED2} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CKE} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MAC_1_MDC} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:LED1} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:ODT} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MAC_1_MDIO} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_STP} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CAN_1_TXBUS} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CK} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_CMODE4} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:LED3} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CS} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MMUART_3_TXD_M2F} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_RESETN} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DATA1} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:LED0} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_CMODE3} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_CMODE6} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DATA0} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CK_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MMUART_1_TXD_M2F} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_CMODE5} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DATA3} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_TXD0_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_ULPI_RESET} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MMUART_0_TXD_M2F} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_SRESET} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DATA2} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_TXD0_P} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_CMODE7} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DATA5} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_TXD1_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:MMUART_2_TXD_M2F} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_PLLMODE} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DATA4} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_TXD1_P} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:VSC_8662_OSCEN} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DATA7} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CAN_0_TXBUS_M2F} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_TXD2_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SGMII_TX0_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:USB_DATA6} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CAN_0_TX_EBL_M2F} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:PCIESS_LANE_TXD2_P} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SGMII_TX0_P} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:RESET_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SGMII_TX1_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:DM} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:DQS_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:DQS} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:DQ} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:CA} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SDIO_SW_EN_N} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:mBUS_UART_TX} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SPI_0_CLK_M2F}
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SPI_0_DO_M2F}  
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SPI_0_SS1_M2F} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:RPi_GPIO12} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:RPI_GPIO16} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:RPI_GPIO20} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:RPI_GPIO21} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:QSPI_CS} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:QSPI_CLK} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_CLK_EMMC_CLK} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_CMD_EMMC_CMD} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_DATA0_EMMC_DATA0} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_DATA1_EMMC_DATA1} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_DATA2_EMMC_DATA2} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_DATA3_EMMC_DATA3} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_POW_EMMC_DATA4} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_VOLT_SEL_EMMC_DATA5} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_VOLT_EN_EMMC_DATA6} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_VOLT_CMD_DIR_EMMC_DATA7} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_VOLT_DIR_1_3_EMMC_UNUSED} 
-sd_mark_pins_unused -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_VOLT_DIR_0_EMMC_UNUSED} 
-sd_mark_pins_unused -sd_name {Test_bench} -pin_names {B_V_F_BASE_DESIGN_0:COREUART_TX} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_CD_EMMC_STRB} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_tb_name} -pin_names {B_V_F_BASE_DESIGN_0:SD_WP_EMMC_RSTN} -value {GND} 
-
-# Generate smart design
-generate_component -component_name ${sd_tb_name} -recursive 0 
-
-# Import stimulus files
-build_design_hierarchy 
-organize_tool_files -tool {SIM_PRESYNTH} -file "$project_dir/component/Actel/Simulation/CLK_GEN/1.0.1/CLK_GEN.v" -file "$project_dir/component/work/CLK_GEN_C0/CLK_GEN_C0.v" -file "$project_dir/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v" -file "$project_dir/component/work/RESET_GEN_C0/RESET_GEN_C0.v" -file "$project_dir/component/work/Test_bench/Test_bench.v" -module {B_V_F_BASE_DESIGN::work} -input_type {stimulus} 
-organize_tool_files -tool {SIM_POSTSYNTH}  -file "$project_dir/component/Actel/Simulation/CLK_GEN/1.0.1/CLK_GEN.v" -file "$project_dir/component/work/CLK_GEN_C0/CLK_GEN_C0.v" -file "$project_dir/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v" -file "$project_dir/component/work/RESET_GEN_C0/RESET_GEN_C0.v" -file "$project_dir/component/work/Test_bench/Test_bench.v" -module {B_V_F_BASE_DESIGN::work} -input_type {stimulus} 
-import_files \
-         -convert_EDN_to_HDL 0 \
-         -library {work} \
-         -simulation "$local_dir/script_support/simulation/Wave.do" -simulation "$local_dir/script_support/simulation/ICICLE_MSS_PFSOC_MSS_FIC0_user.bfm" -simulation "$local_dir/script_support/simulation/ICICLE_MSS_PFSOC_MSS_FIC3_user.bfm"
-         
-# Configure simulation options
-set_modelsim_options  -include_do_file 1 -included_do_file "${project_dir}/simulation/Wave.do" -sim_runtime "10us"

script_support/simulation/Wave.do

-onerror {resume}
-quietly WaveActivateNextPane {} 0
-
-add wave -noupdate -expand -group {Test_bench_LEVEL: ports} /Test_bench/RPi_GPIO5
-add wave -noupdate -expand -group {Test_bench_LEVEL: ports} /Test_bench/RPi_GPIO6
-add wave -noupdate -expand -group {Test_bench_LEVEL: ports} /Test_bench/RPi_GPIO13
-add wave -noupdate -expand -group {Test_bench_LEVEL: ports} /Test_bench/RPi_GPIO19
-add wave -noupdate -expand -group {Test_bench_LEVEL: ports} /Test_bench/B_V_F_BASE_DESIGN_0/MSS/MSS_RESET_N_F2M
-add wave -noupdate -expand -group {Test_bench_LEVEL: ports} /Test_bench/B_V_F_BASE_DESIGN_0/MSS/MSS_RESET_N_M2F 
-add wave -noupdate -expand -group {FABRIC: COREGPIO_C0 (at BaseAddress 0x4200_0000, on FIC3)} /Test_bench/B_V_F_BASE_DESIGN_0/COREGPIO_C0/PCLK
-add wave -noupdate -expand -group {FABRIC: COREGPIO_C0 (at BaseAddress 0x4200_0000, on FIC3)} /Test_bench/B_V_F_BASE_DESIGN_0/COREGPIO_C0/PSEL
-add wave -noupdate -expand -group {FABRIC: COREGPIO_C0 (at BaseAddress 0x4200_0000, on FIC3)} /Test_bench/B_V_F_BASE_DESIGN_0/COREGPIO_C0/PENABLE
-add wave -noupdate -expand -group {FABRIC: COREGPIO_C0 (at BaseAddress 0x4200_0000, on FIC3)} /Test_bench/B_V_F_BASE_DESIGN_0/COREGPIO_C0/PADDR
-add wave -noupdate -expand -group {FABRIC: COREGPIO_C0 (at BaseAddress 0x4200_0000, on FIC3)} /Test_bench/B_V_F_BASE_DESIGN_0/COREGPIO_C0/PWRITE
-add wave -noupdate -expand -group {FABRIC: COREGPIO_C0 (at BaseAddress 0x4200_0000, on FIC3)} /Test_bench/B_V_F_BASE_DESIGN_0/COREGPIO_C0/PWDATA
-add wave -noupdate -expand -group {FABRIC: COREGPIO_C0 (at BaseAddress 0x4200_0000, on FIC3)} /Test_bench/B_V_F_BASE_DESIGN_0/COREGPIO_C0/PREADY
-add wave -noupdate -expand -group {FABRIC: COREGPIO_C0 (at BaseAddress 0x4200_0000, on FIC3)} /Test_bench/B_V_F_BASE_DESIGN_0/COREGPIO_C0/PRDATA
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/ARESETN
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/ACLK
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/AWVALID
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/AWADDR
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/AWREADY
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/ARADDR
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/ARVALID
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/ARREADY
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/BREADY
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/BVALID
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/RDATA
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/RREADY
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/RVALID
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/WDATA
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/WREADY
-add wave -noupdate -expand -group {FABRIC: MSS_LSRAM (at Baseddress 0x6100_0000, on FIC0)} /Test_bench/B_V_F_BASE_DESIGN_0/MSS_LSRAM_inst_0/WVALID
-
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {16493562 ps} 0} {{Cursor 2} {6098277 ps} 0}
-quietly wave cursor active 2
-
-configure wave -namecolwidth 478
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-
-update
-WaveRestoreZoom {5611018 ps} {7579768 ps}