Cape: Verilog template: Re-order cape IOs.
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- sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl 53 additions, 53 deletions...ipt_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
- sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v 22 additions, 22 deletions...cript_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
- sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/P8_IOPADS.v 15 additions, 15 deletions..._support/components/CAPE/VERILOG_TEMPLATE/HDL/P8_IOPADS.v
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