Cape: Verilog template: Simplify APB interface.
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- sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl 0 additions, 2 deletions...ipt_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
- sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v 0 additions, 14 deletions...cript_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
- sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/apb_ctrl_status.v 73 additions, 47 deletions...rt/components/CAPE/VERILOG_TEMPLATE/HDL/apb_ctrl_status.v
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