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Commit 8474b79e authored by Vauban's avatar Vauban
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Cape: Add Verilog template.

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puts "======== Add cape option: VERILOG_TEMPLATE ========"
#-------------------------------------------------------------------------------
# Import HDL source files
#-------------------------------------------------------------------------------
import_files -hdl_source {script_support/components/CAPE/VERILOG_TEMPLATE/HDL/apb_ctrl_status.v}
import_files -hdl_source {script_support/components/CAPE/VERILOG_TEMPLATE/HDL/P8_IOPADS.v}
import_files -hdl_source {script_support/components/CAPE/VERILOG_TEMPLATE/HDL/P9_11_18_IOPADS.v}
import_files -hdl_source {script_support/components/CAPE/VERILOG_TEMPLATE/HDL/P9_21_31_IOPADS.v}
import_files -hdl_source {script_support/components/CAPE/VERILOG_TEMPLATE/HDL/P9_41_42_IOPADS.v}
import_files -hdl_source {script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v}
build_design_hierarchy
create_hdl_core -file $project_dir/hdl/CAPE.v -module {CAPE} -library {work} -package {}
hdl_core_add_bif -hdl_core_name {CAPE} -bif_definition {APB:AMBA:AMBA2:slave} -bif_name {BIF_1} -signal_map {}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PADDR} -core_signal_name {APB_SLAVE_SLAVE_PADDR}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PSELx} -core_signal_name {APB_SLAVE_SLAVE_PSEL}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PENABLE} -core_signal_name {APB_SLAVE_SLAVE_PENABLE}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PWRITE} -core_signal_name {APB_SLAVE_SLAVE_PWRITE}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PRDATA} -core_signal_name {APB_SLAVE_SLAVE_PRDATA}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PWDATA} -core_signal_name {APB_SLAVE_SLAVE_PWDATA}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PREADY} -core_signal_name {APB_SLAVE_SLAVE_PREADY}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PSLVERR} -core_signal_name {APB_SLAVE_SLAVE_PSLVERR}
hdl_core_rename_bif -hdl_core_name {CAPE} -current_bif_name {BIF_1} -new_bif_name {APB_TARGET}
#-------------------------------------------------------------------------------
# Build the Cape module
#-------------------------------------------------------------------------------
set sd_name ${top_level_name}
#-------------------------------------------------------------------------------
# Cape pins
#-------------------------------------------------------------------------------
#-------------------------------------------------------------------------------
# Instantiate.
#-------------------------------------------------------------------------------
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CAPE} -instance_name {CAPE}
#-------------------------------------------------------------------------------
# Connections.
#-------------------------------------------------------------------------------
# Clocks and resets
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "CAPE:PCLK"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "CAPE:PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_F2M" "CAPE:GPIO_IN"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_M2F" "CAPE:GPIO_OUT"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F" "CAPE:GPIO_OE"}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_32} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_30} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_13} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_39} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_10} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_41} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_29} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_27} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_25} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_23} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_21} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_9} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_28} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_6} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_29} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_15} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_7} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_18} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_18} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_26} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_12} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_27} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_42} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_14} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_35} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_16} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_5} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_44} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_24} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_3} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_25} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_41} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_46} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_45} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_22} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_8} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_23} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_42} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_30} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_26} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_24} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_22} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_31} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_4} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_11} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_37} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_16} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_43} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_20} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_38} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_17} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_28} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_14} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_11} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_31} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_19} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_13} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_36} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_15} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_33} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_17} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_12} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_40} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_21} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_34} -port_name {}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_TARGET" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_TXD}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_RXD} -value {GND}
sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -pin_slices {"[26:3]"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M[26:3]" "CAPE:INT"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -pin_slices {"[58:27]"}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M[58:27]} -value {GND}
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Sun Dec 3 10:18:21 2023
// Version: 2022.3 2022.3.0.8
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
// CAPE
module CAPE(
// Inputs
APB_SLAVE_SLAVE_PADDR,
APB_SLAVE_SLAVE_PENABLE,
APB_SLAVE_SLAVE_PSEL,
APB_SLAVE_SLAVE_PWDATA,
APB_SLAVE_SLAVE_PWRITE,
GPIO_OE,
GPIO_OUT,
PCLK,
PRESETN,
// Outputs
APB_SLAVE_SLAVE_PRDATA,
APB_SLAVE_SLAVE_PREADY,
APB_SLAVE_SLAVE_PSLVERR,
GPIO_IN,
INT,
// Inouts
P8_10,
P8_11,
P8_12,
P8_13,
P8_14,
P8_15,
P8_16,
P8_17,
P8_18,
P8_19,
P8_20,
P8_21,
P8_22,
P8_23,
P8_24,
P8_25,
P8_26,
P8_27,
P8_28,
P8_29,
P8_3,
P8_30,
P8_31,
P8_32,
P8_33,
P8_34,
P8_35,
P8_36,
P8_37,
P8_38,
P8_39,
P8_4,
P8_40,
P8_41,
P8_42,
P8_43,
P8_44,
P8_45,
P8_46,
P8_5,
P8_6,
P8_7,
P8_8,
P8_9,
P9_11,
P9_12,
P9_13,
P9_14,
P9_15,
P9_16,
P9_17,
P9_18,
P9_21,
P9_22,
P9_23,
P9_24,
P9_25,
P9_26,
P9_27,
P9_28,
P9_29,
P9_30,
P9_31,
P9_41,
P9_42
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [31:0] APB_SLAVE_SLAVE_PADDR;
input APB_SLAVE_SLAVE_PENABLE;
input APB_SLAVE_SLAVE_PSEL;
input [31:0] APB_SLAVE_SLAVE_PWDATA;
input APB_SLAVE_SLAVE_PWRITE;
input [27:0] GPIO_OE;
input [27:0] GPIO_OUT;
input PCLK;
input PRESETN;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:0] APB_SLAVE_SLAVE_PRDATA;
output APB_SLAVE_SLAVE_PREADY;
output APB_SLAVE_SLAVE_PSLVERR;
output [27:0] GPIO_IN;
output [23:0] INT;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout P8_10;
inout P8_11;
inout P8_12;
inout P8_13;
inout P8_14;
inout P8_15;
inout P8_16;
inout P8_17;
inout P8_18;
inout P8_19;
inout P8_20;
inout P8_21;
inout P8_22;
inout P8_23;
inout P8_24;
inout P8_25;
inout P8_26;
inout P8_27;
inout P8_28;
inout P8_29;
inout P8_3;
inout P8_30;
inout P8_31;
inout P8_32;
inout P8_33;
inout P8_34;
inout P8_35;
inout P8_36;
inout P8_37;
inout P8_38;
inout P8_39;
inout P8_4;
inout P8_40;
inout P8_41;
inout P8_42;
inout P8_43;
inout P8_44;
inout P8_45;
inout P8_46;
inout P8_5;
inout P8_6;
inout P8_7;
inout P8_8;
inout P8_9;
inout P9_11;
inout P9_12;
inout P9_13;
inout P9_14;
inout P9_15;
inout P9_16;
inout P9_17;
inout P9_18;
inout P9_21;
inout P9_22;
inout P9_23;
inout P9_24;
inout P9_25;
inout P9_26;
inout P9_27;
inout P9_28;
inout P9_29;
inout P9_30;
inout P9_31;
inout P9_41;
inout P9_42;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire [31:0] apb_ctrl_status_0_control;
wire APB_SLAVE_SLAVE_PENABLE;
wire [31:0] APB_SLAVE_PRDATA;
wire APB_SLAVE_PREADY;
wire APB_SLAVE_SLAVE_PSEL;
wire APB_SLAVE_PSLVERR;
wire [31:0] APB_SLAVE_SLAVE_PWDATA;
wire APB_SLAVE_SLAVE_PWRITE;
wire [30:3] GPIO_IN_net_0;
wire [27:0] GPIO_OE;
wire [27:0] GPIO_OUT;
wire P8_3;
wire P8_4;
wire P8_5;
wire P8_6;
wire P8_7;
wire P8_8;
wire P8_9;
wire P8_10;
wire P8_11;
wire P8_12;
wire P8_13;
wire P8_14;
wire P8_15;
wire P8_16;
wire P8_17;
wire P8_18;
wire P8_19;
wire P8_20;
wire P8_21;
wire P8_22;
wire P8_23;
wire P8_24;
wire P8_25;
wire P8_26;
wire P8_27;
wire P8_28;
wire P8_29;
wire P8_30;
wire P8_31;
wire P8_32;
wire P8_33;
wire P8_34;
wire P8_35;
wire P8_36;
wire P8_37;
wire P8_38;
wire P8_39;
wire P8_40;
wire P8_41;
wire P8_42;
wire P8_43;
wire P8_44;
wire P8_45;
wire P8_46;
wire P9_11;
wire P9_12;
wire P9_13;
wire P9_14;
wire P9_15;
wire P9_16;
wire P9_17;
wire P9_18;
wire P9_21;
wire P9_22;
wire P9_23;
wire P9_24;
wire P9_25;
wire P9_26;
wire P9_27;
wire P9_28;
wire P9_29;
wire P9_30;
wire P9_31;
wire P9_41;
wire P9_42;
wire PCLK;
wire PRESETN;
wire APB_SLAVE_PREADY_net_0;
wire APB_SLAVE_PSLVERR_net_0;
wire [31:0] APB_SLAVE_PRDATA_net_0;
wire [27:0] GPIO_IN_net_1;
wire [46:31] GPIO_IN_slice_0;
wire [46:3] GPIO_OE_net_0;
wire [46:3] GPIO_OUT_net_0;
wire [46:3] GPIO_IN_net_2;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire [23:0] INT_const_net_0;
wire [46:31] GPIO_OE_const_net_0;
wire [46:31] GPIO_OUT_const_net_0;
wire [18:11] GPIO_OE_const_net_1;
wire [18:11] GPIO_OUT_const_net_1;
wire [31:21] GPIO_OE_const_net_2;
wire [31:21] GPIO_OUT_const_net_2;
wire [42:41] GPIO_OE_const_net_3;
wire [42:41] GPIO_OUT_const_net_3;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire [31:0] APB_SLAVE_SLAVE_PADDR;
wire [7:0] APB_SLAVE_SLAVE_PADDR_0;
wire [7:0] APB_SLAVE_SLAVE_PADDR_0_7to0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign INT_const_net_0 = 24'h000000;
assign GPIO_OE_const_net_0 = 16'h0000;
assign GPIO_OUT_const_net_0 = 16'h0000;
assign GPIO_OE_const_net_1 = 8'h00;
assign GPIO_OUT_const_net_1 = 8'h00;
assign GPIO_OE_const_net_2 = 11'h000;
assign GPIO_OUT_const_net_2 = 11'h000;
assign GPIO_OE_const_net_3 = 2'h0;
assign GPIO_OUT_const_net_3 = 2'h0;
//--------------------------------------------------------------------
// TieOff assignments
//--------------------------------------------------------------------
assign INT[23:0] = 24'h000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign APB_SLAVE_PREADY_net_0 = APB_SLAVE_PREADY;
assign APB_SLAVE_SLAVE_PREADY = APB_SLAVE_PREADY_net_0;
assign APB_SLAVE_PSLVERR_net_0 = APB_SLAVE_PSLVERR;
assign APB_SLAVE_SLAVE_PSLVERR = APB_SLAVE_PSLVERR_net_0;
assign APB_SLAVE_PRDATA_net_0 = APB_SLAVE_PRDATA;
assign APB_SLAVE_SLAVE_PRDATA[31:0] = APB_SLAVE_PRDATA_net_0;
assign GPIO_IN_net_1 = GPIO_IN_net_0;
assign GPIO_IN[27:0] = GPIO_IN_net_1;
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign GPIO_IN_net_0 = GPIO_IN_net_2[30:3];
assign GPIO_IN_slice_0 = GPIO_IN_net_2[46:31];
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign GPIO_OE_net_0 = { 16'h0000 , GPIO_OE };
assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT };
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign APB_SLAVE_SLAVE_PADDR_0 = { APB_SLAVE_SLAVE_PADDR_0_7to0 };
assign APB_SLAVE_SLAVE_PADDR_0_7to0 = APB_SLAVE_SLAVE_PADDR[7:0];
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------apb_ctrl_status
apb_ctrl_status apb_ctrl_status_0(
// Inputs
.presetn ( PRESETN ),
.pclk ( PCLK ),
.psel ( APB_SLAVE_SLAVE_PSEL ),
.penable ( APB_SLAVE_SLAVE_PENABLE ),
.pwrite ( APB_SLAVE_SLAVE_PWRITE ),
.paddr ( APB_SLAVE_SLAVE_PADDR_0 ),
.pwdata ( APB_SLAVE_SLAVE_PWDATA ),
.status ( apb_ctrl_status_0_control ),
// Outputs
.pslverr ( APB_SLAVE_PSLVERR ),
.pready ( APB_SLAVE_PREADY ),
.prdata ( APB_SLAVE_PRDATA ),
.control ( apb_ctrl_status_0_control )
);
//--------P8_IOPADS
P8_IOPADS P8_IOPADS_0(
// Inputs
.GPIO_OE ( GPIO_OE_net_0 ),
.GPIO_OUT ( GPIO_OUT_net_0 ),
// Outputs
.GPIO_IN ( GPIO_IN_net_2 ),
// Inouts
.P8_10 ( P8_10 ),
.P8_11 ( P8_11 ),
.P8_12 ( P8_12 ),
.P8_13 ( P8_13 ),
.P8_14 ( P8_14 ),
.P8_15 ( P8_15 ),
.P8_16 ( P8_16 ),
.P8_17 ( P8_17 ),
.P8_18 ( P8_18 ),
.P8_19 ( P8_19 ),
.P8_20 ( P8_20 ),
.P8_21 ( P8_21 ),
.P8_22 ( P8_22 ),
.P8_23 ( P8_23 ),
.P8_24 ( P8_24 ),
.P8_25 ( P8_25 ),
.P8_26 ( P8_26 ),
.P8_27 ( P8_27 ),
.P8_28 ( P8_28 ),
.P8_29 ( P8_29 ),
.P8_3 ( P8_3 ),
.P8_30 ( P8_30 ),
.P8_31 ( P8_31 ),
.P8_32 ( P8_32 ),
.P8_33 ( P8_33 ),
.P8_34 ( P8_34 ),
.P8_35 ( P8_35 ),
.P8_36 ( P8_36 ),
.P8_37 ( P8_37 ),
.P8_38 ( P8_38 ),
.P8_39 ( P8_39 ),
.P8_4 ( P8_4 ),
.P8_40 ( P8_40 ),
.P8_41 ( P8_41 ),
.P8_42 ( P8_42 ),
.P8_43 ( P8_43 ),
.P8_44 ( P8_44 ),
.P8_45 ( P8_45 ),
.P8_46 ( P8_46 ),
.P8_5 ( P8_5 ),
.P8_6 ( P8_6 ),
.P8_7 ( P8_7 ),
.P8_8 ( P8_8 ),
.P8_9 ( P8_9 )
);
//--------P9_11_18_IOPADS
P9_11_18_IOPADS P9_11_18_IOPADS_0(
// Inputs
.GPIO_OE ( GPIO_OE_const_net_1 ),
.GPIO_OUT ( GPIO_OUT_const_net_1 ),
// Outputs
.GPIO_IN ( ),
// Inouts
.P9_11 ( P9_11 ),
.P9_12 ( P9_12 ),
.P9_13 ( P9_13 ),
.P9_14 ( P9_14 ),
.P9_15 ( P9_15 ),
.P9_16 ( P9_16 ),
.P9_17 ( P9_17 ),
.P9_18 ( P9_18 )
);
//--------P9_21_31_IOPADS
P9_21_31_IOPADS P9_21_31_IOPADS_0(
// Inputs
.GPIO_OE ( GPIO_OE_const_net_2 ),
.GPIO_OUT ( GPIO_OUT_const_net_2 ),
// Outputs
.GPIO_IN ( ),
// Inouts
.P9_21 ( P9_21 ),
.P9_22 ( P9_22 ),
.P9_23 ( P9_23 ),
.P9_24 ( P9_24 ),
.P9_25 ( P9_25 ),
.P9_26 ( P9_26 ),
.P9_27 ( P9_27 ),
.P9_28 ( P9_28 ),
.P9_29 ( P9_29 ),
.P9_30 ( P9_30 ),
.P9_31 ( P9_31 )
);
//--------P9_41_42_IOPADS
P9_41_42_IOPADS P9_41_42_IOPADS_0(
// Inputs
.GPIO_OE ( GPIO_OE_const_net_3 ),
.GPIO_OUT ( GPIO_OUT_const_net_3 ),
// Outputs
.GPIO_IN ( ),
// Inouts
.P9_41 ( P9_41 ),
.P9_42 ( P9_42 )
);
endmodule
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Sat Dec 2 16:38:15 2023
// Version: 2022.3 2022.3.0.8
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
// P9_11_18_IOPADS
module P9_11_18_IOPADS(
// Inputs
GPIO_OE,
GPIO_OUT,
// Outputs
GPIO_IN,
// Inouts
P9_11,
P9_12,
P9_13,
P9_14,
P9_15,
P9_16,
P9_17,
P9_18
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [18:11] GPIO_OE;
input [18:11] GPIO_OUT;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [18:11] GPIO_IN;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout P9_11;
inout P9_12;
inout P9_13;
inout P9_14;
inout P9_15;
inout P9_16;
inout P9_17;
inout P9_18;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire GPIO_IN_net_0;
wire GPIO_IN_0;
wire GPIO_IN_1;
wire GPIO_IN_2;
wire GPIO_IN_3;
wire GPIO_IN_4;
wire GPIO_IN_5;
wire GPIO_IN_6;
wire [11:11] GPIO_OE_slice_0;
wire [12:12] GPIO_OE_slice_1;
wire [13:13] GPIO_OE_slice_2;
wire [14:14] GPIO_OE_slice_3;
wire [15:15] GPIO_OE_slice_4;
wire [16:16] GPIO_OE_slice_5;
wire [17:17] GPIO_OE_slice_6;
wire [18:18] GPIO_OE_slice_7;
wire [11:11] GPIO_OUT_slice_0;
wire [12:12] GPIO_OUT_slice_1;
wire [13:13] GPIO_OUT_slice_2;
wire [14:14] GPIO_OUT_slice_3;
wire [15:15] GPIO_OUT_slice_4;
wire [16:16] GPIO_OUT_slice_5;
wire [17:17] GPIO_OUT_slice_6;
wire [18:18] GPIO_OUT_slice_7;
wire P9_11;
wire P9_12;
wire P9_13;
wire P9_14;
wire P9_15;
wire P9_16;
wire P9_17;
wire P9_18;
wire [11:11] GPIO_IN_net_1;
wire [12:12] GPIO_IN_0_net_0;
wire [13:13] GPIO_IN_1_net_0;
wire [14:14] GPIO_IN_2_net_0;
wire [15:15] GPIO_IN_3_net_0;
wire [16:16] GPIO_IN_4_net_0;
wire [17:17] GPIO_IN_5_net_0;
wire [18:18] GPIO_IN_6_net_0;
wire [18:11] GPIO_OUT;
wire [18:11] GPIO_OE;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign GPIO_IN_net_1[11] = GPIO_IN_net_0;
assign GPIO_IN[11:11] = GPIO_IN_net_1[11];
assign GPIO_IN_0_net_0[12] = GPIO_IN_0;
assign GPIO_IN[12:12] = GPIO_IN_0_net_0[12];
assign GPIO_IN_1_net_0[13] = GPIO_IN_1;
assign GPIO_IN[13:13] = GPIO_IN_1_net_0[13];
assign GPIO_IN_2_net_0[14] = GPIO_IN_2;
assign GPIO_IN[14:14] = GPIO_IN_2_net_0[14];
assign GPIO_IN_3_net_0[15] = GPIO_IN_3;
assign GPIO_IN[15:15] = GPIO_IN_3_net_0[15];
assign GPIO_IN_4_net_0[16] = GPIO_IN_4;
assign GPIO_IN[16:16] = GPIO_IN_4_net_0[16];
assign GPIO_IN_5_net_0[17] = GPIO_IN_5;
assign GPIO_IN[17:17] = GPIO_IN_5_net_0[17];
assign GPIO_IN_6_net_0[18] = GPIO_IN_6;
assign GPIO_IN[18:18] = GPIO_IN_6_net_0[18];
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign GPIO_OE_slice_0[11] = GPIO_OE[11:11];
assign GPIO_OE_slice_1[12] = GPIO_OE[12:12];
assign GPIO_OE_slice_2[13] = GPIO_OE[13:13];
assign GPIO_OE_slice_3[14] = GPIO_OE[14:14];
assign GPIO_OE_slice_4[15] = GPIO_OE[15:15];
assign GPIO_OE_slice_5[16] = GPIO_OE[16:16];
assign GPIO_OE_slice_6[17] = GPIO_OE[17:17];
assign GPIO_OE_slice_7[18] = GPIO_OE[18:18];
assign GPIO_OUT_slice_0[11] = GPIO_OUT[11:11];
assign GPIO_OUT_slice_1[12] = GPIO_OUT[12:12];
assign GPIO_OUT_slice_2[13] = GPIO_OUT[13:13];
assign GPIO_OUT_slice_3[14] = GPIO_OUT[14:14];
assign GPIO_OUT_slice_4[15] = GPIO_OUT[15:15];
assign GPIO_OUT_slice_5[16] = GPIO_OUT[16:16];
assign GPIO_OUT_slice_6[17] = GPIO_OUT[17:17];
assign GPIO_OUT_slice_7[18] = GPIO_OUT[18:18];
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------BIBUF
BIBUF P9_11_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_0 ),
.E ( GPIO_OE_slice_0 ),
// Outputs
.Y ( GPIO_IN_net_0 ),
// Inouts
.PAD ( P9_11 )
);
//--------BIBUF
BIBUF P9_12_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_1 ),
.E ( GPIO_OE_slice_1 ),
// Outputs
.Y ( GPIO_IN_0 ),
// Inouts
.PAD ( P9_12 )
);
//--------BIBUF
BIBUF P9_13_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_2 ),
.E ( GPIO_OE_slice_2 ),
// Outputs
.Y ( GPIO_IN_1 ),
// Inouts
.PAD ( P9_13 )
);
//--------BIBUF
BIBUF P9_14_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_3 ),
.E ( GPIO_OE_slice_3 ),
// Outputs
.Y ( GPIO_IN_2 ),
// Inouts
.PAD ( P9_14 )
);
//--------BIBUF
BIBUF P9_15_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_4 ),
.E ( GPIO_OE_slice_4 ),
// Outputs
.Y ( GPIO_IN_3 ),
// Inouts
.PAD ( P9_15 )
);
//--------BIBUF
BIBUF P9_16_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_5 ),
.E ( GPIO_OE_slice_5 ),
// Outputs
.Y ( GPIO_IN_4 ),
// Inouts
.PAD ( P9_16 )
);
//--------BIBUF
BIBUF P9_17_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_6 ),
.E ( GPIO_OE_slice_6 ),
// Outputs
.Y ( GPIO_IN_5 ),
// Inouts
.PAD ( P9_17 )
);
//--------BIBUF
BIBUF P9_18_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_7 ),
.E ( GPIO_OE_slice_7 ),
// Outputs
.Y ( GPIO_IN_6 ),
// Inouts
.PAD ( P9_18 )
);
endmodule
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Sat Dec 2 16:38:15 2023
// Version: 2022.3 2022.3.0.8
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
// P9_21_31_IOPADS
module P9_21_31_IOPADS(
// Inputs
GPIO_OE,
GPIO_OUT,
// Outputs
GPIO_IN,
// Inouts
P9_21,
P9_22,
P9_23,
P9_24,
P9_25,
P9_26,
P9_27,
P9_28,
P9_29,
P9_30,
P9_31
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [31:21] GPIO_OE;
input [31:21] GPIO_OUT;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:21] GPIO_IN;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout P9_21;
inout P9_22;
inout P9_23;
inout P9_24;
inout P9_25;
inout P9_26;
inout P9_27;
inout P9_28;
inout P9_29;
inout P9_30;
inout P9_31;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire GPIO_IN_net_0;
wire GPIO_IN_0;
wire GPIO_IN_1;
wire GPIO_IN_2;
wire GPIO_IN_3;
wire GPIO_IN_4;
wire GPIO_IN_5;
wire GPIO_IN_6;
wire GPIO_IN_7;
wire GPIO_IN_8;
wire GPIO_IN_9;
wire [21:21] GPIO_OE_slice_0;
wire [22:22] GPIO_OE_slice_1;
wire [23:23] GPIO_OE_slice_2;
wire [24:24] GPIO_OE_slice_3;
wire [25:25] GPIO_OE_slice_4;
wire [26:26] GPIO_OE_slice_5;
wire [27:27] GPIO_OE_slice_6;
wire [28:28] GPIO_OE_slice_7;
wire [29:29] GPIO_OE_slice_8;
wire [30:30] GPIO_OE_slice_9;
wire [31:31] GPIO_OE_slice_10;
wire [21:21] GPIO_OUT_slice_0;
wire [22:22] GPIO_OUT_slice_1;
wire [23:23] GPIO_OUT_slice_2;
wire [24:24] GPIO_OUT_slice_3;
wire [25:25] GPIO_OUT_slice_4;
wire [26:26] GPIO_OUT_slice_5;
wire [27:27] GPIO_OUT_slice_6;
wire [28:28] GPIO_OUT_slice_7;
wire [29:29] GPIO_OUT_slice_8;
wire [30:30] GPIO_OUT_slice_9;
wire [31:31] GPIO_OUT_slice_10;
wire P9_21;
wire P9_22;
wire P9_23;
wire P9_24;
wire P9_25;
wire P9_26;
wire P9_27;
wire P9_28;
wire P9_29;
wire P9_30;
wire P9_31;
wire [21:21] GPIO_IN_net_1;
wire [22:22] GPIO_IN_0_net_0;
wire [23:23] GPIO_IN_1_net_0;
wire [24:24] GPIO_IN_2_net_0;
wire [25:25] GPIO_IN_3_net_0;
wire [26:26] GPIO_IN_4_net_0;
wire [27:27] GPIO_IN_5_net_0;
wire [28:28] GPIO_IN_6_net_0;
wire [29:29] GPIO_IN_7_net_0;
wire [30:30] GPIO_IN_8_net_0;
wire [31:31] GPIO_IN_9_net_0;
wire [31:21] GPIO_OUT;
wire [31:21] GPIO_OE;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign GPIO_IN_net_1[21] = GPIO_IN_net_0;
assign GPIO_IN[21:21] = GPIO_IN_net_1[21];
assign GPIO_IN_0_net_0[22] = GPIO_IN_0;
assign GPIO_IN[22:22] = GPIO_IN_0_net_0[22];
assign GPIO_IN_1_net_0[23] = GPIO_IN_1;
assign GPIO_IN[23:23] = GPIO_IN_1_net_0[23];
assign GPIO_IN_2_net_0[24] = GPIO_IN_2;
assign GPIO_IN[24:24] = GPIO_IN_2_net_0[24];
assign GPIO_IN_3_net_0[25] = GPIO_IN_3;
assign GPIO_IN[25:25] = GPIO_IN_3_net_0[25];
assign GPIO_IN_4_net_0[26] = GPIO_IN_4;
assign GPIO_IN[26:26] = GPIO_IN_4_net_0[26];
assign GPIO_IN_5_net_0[27] = GPIO_IN_5;
assign GPIO_IN[27:27] = GPIO_IN_5_net_0[27];
assign GPIO_IN_6_net_0[28] = GPIO_IN_6;
assign GPIO_IN[28:28] = GPIO_IN_6_net_0[28];
assign GPIO_IN_7_net_0[29] = GPIO_IN_7;
assign GPIO_IN[29:29] = GPIO_IN_7_net_0[29];
assign GPIO_IN_8_net_0[30] = GPIO_IN_8;
assign GPIO_IN[30:30] = GPIO_IN_8_net_0[30];
assign GPIO_IN_9_net_0[31] = GPIO_IN_9;
assign GPIO_IN[31:31] = GPIO_IN_9_net_0[31];
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign GPIO_OE_slice_0[21] = GPIO_OE[21:21];
assign GPIO_OE_slice_1[22] = GPIO_OE[22:22];
assign GPIO_OE_slice_2[23] = GPIO_OE[23:23];
assign GPIO_OE_slice_3[24] = GPIO_OE[24:24];
assign GPIO_OE_slice_4[25] = GPIO_OE[25:25];
assign GPIO_OE_slice_5[26] = GPIO_OE[26:26];
assign GPIO_OE_slice_6[27] = GPIO_OE[27:27];
assign GPIO_OE_slice_7[28] = GPIO_OE[28:28];
assign GPIO_OE_slice_8[29] = GPIO_OE[29:29];
assign GPIO_OE_slice_9[30] = GPIO_OE[30:30];
assign GPIO_OE_slice_10[31] = GPIO_OE[31:31];
assign GPIO_OUT_slice_0[21] = GPIO_OUT[21:21];
assign GPIO_OUT_slice_1[22] = GPIO_OUT[22:22];
assign GPIO_OUT_slice_2[23] = GPIO_OUT[23:23];
assign GPIO_OUT_slice_3[24] = GPIO_OUT[24:24];
assign GPIO_OUT_slice_4[25] = GPIO_OUT[25:25];
assign GPIO_OUT_slice_5[26] = GPIO_OUT[26:26];
assign GPIO_OUT_slice_6[27] = GPIO_OUT[27:27];
assign GPIO_OUT_slice_7[28] = GPIO_OUT[28:28];
assign GPIO_OUT_slice_8[29] = GPIO_OUT[29:29];
assign GPIO_OUT_slice_9[30] = GPIO_OUT[30:30];
assign GPIO_OUT_slice_10[31] = GPIO_OUT[31:31];
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------BIBUF
BIBUF P9_21_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_0 ),
.E ( GPIO_OE_slice_0 ),
// Outputs
.Y ( GPIO_IN_net_0 ),
// Inouts
.PAD ( P9_21 )
);
//--------BIBUF
BIBUF P9_22_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_1 ),
.E ( GPIO_OE_slice_1 ),
// Outputs
.Y ( GPIO_IN_0 ),
// Inouts
.PAD ( P9_22 )
);
//--------BIBUF
BIBUF P9_23_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_2 ),
.E ( GPIO_OE_slice_2 ),
// Outputs
.Y ( GPIO_IN_1 ),
// Inouts
.PAD ( P9_23 )
);
//--------BIBUF
BIBUF P9_24_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_3 ),
.E ( GPIO_OE_slice_3 ),
// Outputs
.Y ( GPIO_IN_2 ),
// Inouts
.PAD ( P9_24 )
);
//--------BIBUF
BIBUF P9_25_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_4 ),
.E ( GPIO_OE_slice_4 ),
// Outputs
.Y ( GPIO_IN_3 ),
// Inouts
.PAD ( P9_25 )
);
//--------BIBUF
BIBUF P9_26_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_5 ),
.E ( GPIO_OE_slice_5 ),
// Outputs
.Y ( GPIO_IN_4 ),
// Inouts
.PAD ( P9_26 )
);
//--------BIBUF
BIBUF P9_27_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_6 ),
.E ( GPIO_OE_slice_6 ),
// Outputs
.Y ( GPIO_IN_5 ),
// Inouts
.PAD ( P9_27 )
);
//--------BIBUF
BIBUF P9_28_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_7 ),
.E ( GPIO_OE_slice_7 ),
// Outputs
.Y ( GPIO_IN_6 ),
// Inouts
.PAD ( P9_28 )
);
//--------BIBUF
BIBUF P9_29_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_8 ),
.E ( GPIO_OE_slice_8 ),
// Outputs
.Y ( GPIO_IN_7 ),
// Inouts
.PAD ( P9_29 )
);
//--------BIBUF
BIBUF P9_30_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_9 ),
.E ( GPIO_OE_slice_9 ),
// Outputs
.Y ( GPIO_IN_8 ),
// Inouts
.PAD ( P9_30 )
);
//--------BIBUF
BIBUF P9_31_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_10 ),
.E ( GPIO_OE_slice_10 ),
// Outputs
.Y ( GPIO_IN_9 ),
// Inouts
.PAD ( P9_31 )
);
endmodule
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Sat Dec 2 16:38:15 2023
// Version: 2022.3 2022.3.0.8
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
// P9_41_42_IOPADS
module P9_41_42_IOPADS(
// Inputs
GPIO_OE,
GPIO_OUT,
// Outputs
GPIO_IN,
// Inouts
P9_41,
P9_42
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [42:41] GPIO_OE;
input [42:41] GPIO_OUT;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [42:41] GPIO_IN;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout P9_41;
inout P9_42;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire GPIO_IN_net_0;
wire GPIO_IN_0;
wire [41:41] GPIO_OE_slice_0;
wire [42:42] GPIO_OE_slice_1;
wire [41:41] GPIO_OUT_slice_0;
wire [42:42] GPIO_OUT_slice_1;
wire P9_41;
wire P9_42;
wire [41:41] GPIO_IN_net_1;
wire [42:42] GPIO_IN_0_net_0;
wire [42:41] GPIO_OUT;
wire [42:41] GPIO_OE;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign GPIO_IN_net_1[41] = GPIO_IN_net_0;
assign GPIO_IN[41:41] = GPIO_IN_net_1[41];
assign GPIO_IN_0_net_0[42] = GPIO_IN_0;
assign GPIO_IN[42:42] = GPIO_IN_0_net_0[42];
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign GPIO_OE_slice_0[41] = GPIO_OE[41:41];
assign GPIO_OE_slice_1[42] = GPIO_OE[42:42];
assign GPIO_OUT_slice_0[41] = GPIO_OUT[41:41];
assign GPIO_OUT_slice_1[42] = GPIO_OUT[42:42];
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------BIBUF
BIBUF P9_41_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_0 ),
.E ( GPIO_OE_slice_0 ),
// Outputs
.Y ( GPIO_IN_net_0 ),
// Inouts
.PAD ( P9_41 )
);
//--------BIBUF
BIBUF P9_42_BIBUF(
// Inputs
.D ( GPIO_OUT_slice_1 ),
.E ( GPIO_OE_slice_1 ),
// Outputs
.Y ( GPIO_IN_0 ),
// Inouts
.PAD ( P9_42 )
);
endmodule
module apb_ctrl_status
(
input presetn,
input pclk,
input psel,
input penable,
input pwrite,
output pslverr,
output pready,
input [7:0] paddr,
input [31:0] pwdata,
output [31:0] prdata,
input [31:0] status,
output [31:0] control
);
reg [31:0] control_value;
reg [31:0] status_value_o;
assign pslverr = 1'b0;
assign pready = 1'b1;
assign control = control_value;
assign prdata = ((paddr[7:0] == 8'h20)) ? status_value_o[31:0] : 32'h00000000;
//---------------------------------------------------------------------------
always @(negedge pclk)
begin
if ((psel == 1'b1) & (pwrite == 1'b1) & (penable == 1'b1))
begin
case (paddr)
8'h00: control_value <= 32'h00000001;
8'h10: control_value <= 32'h00000002;
default: control_value <= 32'h00000000;
endcase
end
end
//---------------------------------------------------------------------------
always @(negedge pclk)
begin
status_value_o <= status;
end
endmodule
set_io -port_name P9_11 \
-pin_name B5 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_12 \
-pin_name C5 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_13 \
-pin_name D19 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_14 \
-pin_name C6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
set_io -port_name P9_15 \
-pin_name A5 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_16 \
-pin_name A6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
set_io -port_name P9_17 \
-pin_name C9 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
set_io -port_name P9_18 \
-pin_name C10 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
set_io -port_name P9_21 \
-pin_name B8 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_22 \
-pin_name A8 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_23 \
-pin_name C12 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_24 \
-pin_name B12 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_25 \
-pin_name B7 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_26 \
-pin_name A7 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_27 \
-pin_name D11 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INPUT
set_io -port_name P9_28 \
-pin_name C11 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INPUT
set_io -port_name P9_29 \
-pin_name F17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INPUT
set_io -port_name P9_30 \
-pin_name F16 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_31 \
-pin_name E18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_41 \
-pin_name E15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_42 \
-pin_name E14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INPUT
#-------------------------------------------------------------------------------
set_io -port_name P8_3 \
-pin_name V22 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_4 \
-pin_name W22 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_5 \
-pin_name V19 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_6 \
-pin_name V20 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_7 \
-pin_name V15 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_8 \
-pin_name V14 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_9 \
-pin_name V21 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_10 \
-pin_name W21 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_11 \
-pin_name Y21 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_12 \
-pin_name Y20 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_13 \
-pin_name B10 \
-fixed true \
-io_std LVCMOS33 \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_14 \
-pin_name B9 \
-fixed true \
-io_std LVCMOS33 \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_15 \
-pin_name T12 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_16 \
-pin_name U12 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_17 \
-pin_name W13 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_18 \
-pin_name T16 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_19 \
-pin_name W18 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_20 \
-pin_name R16 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_21 \
-pin_name AA21 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_22 \
-pin_name AA22 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_23 \
-pin_name AB18 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_24 \
-pin_name AA18 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_25 \
-pin_name V17 \
-fixed true \
-OUT_DRIVE 12 \
-RES_PULL None \
-DIRECTION INOUT
set_io -port_name P8_26 \
-pin_name A12 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_27 \
-pin_name A13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_28 \
-pin_name B14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_29 \
-pin_name B13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_30 \
-pin_name D14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_31 \
-pin_name D13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_32 \
-pin_name B15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_33 \
-pin_name A15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INPUT
set_io -port_name P8_34 \
-pin_name C15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_35 \
-pin_name C14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INPUT
set_io -port_name P8_36 \
-pin_name B4 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_37 \
-pin_name C4 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_38 \
-pin_name C17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_39 \
-pin_name B17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_40 \
-pin_name B18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_41 \
-pin_name A18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_42 \
-pin_name D6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_43 \
-pin_name D7 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_44 \
-pin_name D8 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_45 \
-pin_name D9 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_46 \
-pin_name D18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2023 Microchip Technology Inc */
/dts-v1/;
/plugin/;
&{/chosen} {
overlays {
VERILOG-CAPE-GATEWARE = "GATEWARE_GIT_VERSION";
};
};
&{/} {
fabric-bus@40000000 {
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
#gpio-cells = <2>;
ngpios=<16>;
status = "okay";
interrupts = <129>, <130>, <131>, <132>,
<133>, <134>, <135>, <136>,
<137>, <138>, <139>, <140>,
<141>, <142>, <143>, <144>;
gpio-line-names = "P8_31", "P8_32", "", "P8_34",
"", "P8_36", "P8_37", "P8_38",
"P8_39", "P8_40", "P8_41", "P8_42",
"P8_43", "P8_44", "P8_45", "P8_46";
};
};
};
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