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Commit ad2a1c42 authored by Vauban's avatar Vauban
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Cape: Verilog template: Re-order cape IOs.

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sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
+ 53
− 53
View file @ ad2a1c42
......@@ -50,71 +50,71 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_F2M"
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_M2F" "CAPE:GPIO_OUT"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F" "CAPE:GPIO_OE"}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_32} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_30} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_13} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_39} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_10} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_41} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_29} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_27} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_25} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_23} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_21} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_9} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_28} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_3} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_4} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_5} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_6} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_29} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_15} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_7} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_8} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_9} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_10} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_11} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_12} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_13} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_14} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_15} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_16} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_17} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_18} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_18} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_19} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_20} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_21} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_22} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_23} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_24} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_25} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_26} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_12} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_27} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_42} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_14} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_28} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_29} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_30} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_31} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_32} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_33} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_34} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_35} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_16} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_5} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_44} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_24} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_3} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_25} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_41} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_46} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_45} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_22} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_8} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_23} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_42} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_30} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_26} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_24} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_22} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_31} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_4} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_11} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_36} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_37} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_16} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_43} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_20} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_38} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_17} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_28} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_14} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_39} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_40} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_41} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_42} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_43} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_44} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_45} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_46} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_11} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_31} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_19} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_12} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_13} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_36} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_14} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_15} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_33} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_16} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_17} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_12} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_40} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_21} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_34} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_18} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_21} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_22} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_23} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_24} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_25} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_26} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_27} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_28} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_29} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_30} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_31} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_41} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_42} -port_name {}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_TARGET" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
......
sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
+ 22
− 22
View file @ ad2a1c42
......@@ -22,6 +22,13 @@ module CAPE(
GPIO_IN,
INT,
// Inouts
P8_3,
P8_4,
P8_5,
P8_6,
P8_7,
P8_8,
P8_9,
P8_10,
P8_11,
P8_12,
......@@ -42,7 +49,6 @@ module CAPE(
P8_27,
P8_28,
P8_29,
P8_3,
P8_30,
P8_31,
P8_32,
......@@ -53,7 +59,6 @@ module CAPE(
P8_37,
P8_38,
P8_39,
P8_4,
P8_40,
P8_41,
P8_42,
......@@ -61,11 +66,6 @@ module CAPE(
P8_44,
P8_45,
P8_46,
P8_5,
P8_6,
P8_7,
P8_8,
P8_9,
P9_11,
P9_12,
P9_13,
......@@ -110,6 +110,13 @@ output [23:0] INT;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout P8_3;
inout P8_4;
inout P8_5;
inout P8_6;
inout P8_7;
inout P8_8;
inout P8_9;
inout P8_10;
inout P8_11;
inout P8_12;
......@@ -130,7 +137,6 @@ inout P8_26;
inout P8_27;
inout P8_28;
inout P8_29;
inout P8_3;
inout P8_30;
inout P8_31;
inout P8_32;
......@@ -141,7 +147,6 @@ inout P8_36;
inout P8_37;
inout P8_38;
inout P8_39;
inout P8_4;
inout P8_40;
inout P8_41;
inout P8_42;
......@@ -149,11 +154,6 @@ inout P8_43;
inout P8_44;
inout P8_45;
inout P8_46;
inout P8_5;
inout P8_6;
inout P8_7;
inout P8_8;
inout P8_9;
inout P9_11;
inout P9_12;
inout P9_13;
......@@ -344,6 +344,13 @@ P8_IOPADS P8_IOPADS_0(
// Outputs
.GPIO_IN ( GPIO_IN_net_2 ),
// Inouts
.P8_3 ( P8_3 ),
.P8_4 ( P8_4 ),
.P8_5 ( P8_5 ),
.P8_6 ( P8_6 ),
.P8_7 ( P8_7 ),
.P8_8 ( P8_8 ),
.P8_9 ( P8_9 ),
.P8_10 ( P8_10 ),
.P8_11 ( P8_11 ),
.P8_12 ( P8_12 ),
......@@ -364,7 +371,6 @@ P8_IOPADS P8_IOPADS_0(
.P8_27 ( P8_27 ),
.P8_28 ( P8_28 ),
.P8_29 ( P8_29 ),
.P8_3 ( P8_3 ),
.P8_30 ( P8_30 ),
.P8_31 ( P8_31 ),
.P8_32 ( P8_32 ),
......@@ -375,19 +381,13 @@ P8_IOPADS P8_IOPADS_0(
.P8_37 ( P8_37 ),
.P8_38 ( P8_38 ),
.P8_39 ( P8_39 ),
.P8_4 ( P8_4 ),
.P8_40 ( P8_40 ),
.P8_41 ( P8_41 ),
.P8_42 ( P8_42 ),
.P8_43 ( P8_43 ),
.P8_44 ( P8_44 ),
.P8_45 ( P8_45 ),
.P8_46 ( P8_46 ),
.P8_5 ( P8_5 ),
.P8_6 ( P8_6 ),
.P8_7 ( P8_7 ),
.P8_8 ( P8_8 ),
.P8_9 ( P8_9 )
.P8_46 ( P8_46 )
);
//--------P9_11_18_IOPADS
......
sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/P8_IOPADS.v
+ 15
− 15
View file @ ad2a1c42
......@@ -13,6 +13,13 @@ module P8_IOPADS(
// Outputs
GPIO_IN,
// Inouts
P8_3,
P8_4,
P8_5,
P8_6,
P8_7,
P8_8,
P8_9,
P8_10,
P8_11,
P8_12,
......@@ -33,7 +40,6 @@ module P8_IOPADS(
P8_27,
P8_28,
P8_29,
P8_3,
P8_30,
P8_31,
P8_32,
......@@ -44,19 +50,13 @@ module P8_IOPADS(
P8_37,
P8_38,
P8_39,
P8_4,
P8_40,
P8_41,
P8_42,
P8_43,
P8_44,
P8_45,
P8_46,
P8_5,
P8_6,
P8_7,
P8_8,
P8_9
P8_46
);
//--------------------------------------------------------------------
......@@ -71,6 +71,13 @@ output [46:3] GPIO_IN;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout P8_3;
inout P8_4;
inout P8_5;
inout P8_6;
inout P8_7;
inout P8_8;
inout P8_9;
inout P8_10;
inout P8_11;
inout P8_12;
......@@ -91,7 +98,6 @@ inout P8_26;
inout P8_27;
inout P8_28;
inout P8_29;
inout P8_3;
inout P8_30;
inout P8_31;
inout P8_32;
......@@ -102,7 +108,6 @@ inout P8_36;
inout P8_37;
inout P8_38;
inout P8_39;
inout P8_4;
inout P8_40;
inout P8_41;
inout P8_42;
......@@ -110,11 +115,6 @@ inout P8_43;
inout P8_44;
inout P8_45;
inout P8_46;
inout P8_5;
inout P8_6;
inout P8_7;
inout P8_8;
inout P8_9;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
......
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