- Add PLL to generate 4.915MHz clock for ADC_MCLK.
  - Connect ADC interrupt to MSS GPIO 1 input 20.

  - Move PCIe and closely associated block out of top level design into
    a new sublock containing all FPGA fabric components related to the
    M.2 interface.

Add place holder MIPI CSI interface for the purpose of validating board pin assignment choices.

Use PolarFire SoC Icicle Kit Reference Design as starting point:
  https://github.com/polarfire-soc/icicle-kit-reference-design
  hash: 4c95670cc11bd428d6bec592058f7e86b7b4fa94