ADC: Add clock and interrupt
- Add PLL to generate 4.915MHz clock for ADC_MCLK. - Connect ADC interrupt to MSS GPIO 1 input 20.
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- script_support/B_V_F_recursive.tcl 1 addition, 0 deletionsscript_support/B_V_F_recursive.tcl
- script_support/PF_SoC_MSS_Icicle.cfg 1 addition, 1 deletionscript_support/PF_SoC_MSS_Icicle.cfg
- script_support/components/ADC_MCLK_CCC.tcl 70 additions, 0 deletionsscript_support/components/ADC_MCLK_CCC.tcl
- script_support/components/B_V_F_BASE_DESIGN.tcl 6 additions, 10 deletionsscript_support/components/B_V_F_BASE_DESIGN.tcl
- script_support/components/CLOCKS_AND_RESETS.tcl 8 additions, 0 deletionsscript_support/components/CLOCKS_AND_RESETS.tcl
- script_support/constraints/base_design.pdc 6 additions, 0 deletionsscript_support/constraints/base_design.pdc
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