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Commit 3acbf6dc authored by Vauban's avatar Vauban
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Added cape block.

parent 84ca0b8f
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script_support/MPFS_ICICLE_recursive.tcl
+ 5
− 0
View file @ 3acbf6dc
......@@ -29,5 +29,10 @@ source script_support/components/CoreUARTapb_C0.tcl
source script_support/components/CLOCKS_AND_RESETS.tcl
source script_support/components/IHC_APB.tcl
source script_support/components/IHC_SUBSYSTEM.tcl
source script_support/components/APB_BUS_CONVERTER.tcl
source script_support/components/P8_GPIO_LCD.tcl
source script_support/components/CAPE_DEFAULT_GPIOS.tcl
source script_support/components/CAPE_PWM.tcl
source script_support/components/CAPE.tcl
source script_support/components/MPFS_ICICLE_BASE_DESIGN.tcl
set_root -module {MPFS_ICICLE_KIT_BASE_DESIGN::work}
script_support/components/APB_BUS_CONVERTER.tcl 0 → 100644
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# Creating SmartDesign APB_BUS_CONVERTER
set sd_name {APB_BUS_CONVERTER}
create_smartdesign -sd_name ${sd_name}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE_PADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PENABLE} -port_direction {IN}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE_PRDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PSEL} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PSLVERR} -port_direction {OUT}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE_PWDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PWRITE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PREADY} -port_direction {OUT}
sd_create_bus_port -sd_name ${sd_name} -port_name {MASTER_PADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PENABLE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PWRITE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PSEL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PSLVERR} -port_direction {IN}
sd_create_bus_port -sd_name ${sd_name} -port_name {MASTER_PWDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MASTER_PRDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PREADY} -port_direction {IN}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PADDR" "SLAVE_PADDR"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PENABLE" "SLAVE_PENABLE"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PWRITE" "SLAVE_PWRITE"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PSEL" "SLAVE_PSEL"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PSLVERR" "SLAVE_PSLVERR"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PWDATA" "SLAVE_PWDATA"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PRDATA" "SLAVE_PRDATA"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PREADY" "SLAVE_PREADY"}
sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\ "PADDR:SLAVE_PADDR" \
"PSELx:SLAVE_PSEL" \ "PENABLE:SLAVE_PENABLE" \
"PWRITE:SLAVE_PWRITE" \ "PRDATA:SLAVE_PRDATA" \ "PWDATA:SLAVE_PWDATA" \ "PREADY:SLAVE_PREADY" \
"PSLVERR:SLAVE_PSLVERR" }
sd_create_bif_port -sd_name ${sd_name} -port_name {APB_MASTER} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {master} -port_bif_mapping {\ "PADDR:MASTER_PADDR" \
"PSELx:MASTER_PSEL" \ "PENABLE:MASTER_PENABLE" \
"PWRITE:MASTER_PWRITE" \ "PRDATA:MASTER_PRDATA" \ "PWDATA:MASTER_PWDATA" \ "PREADY:MASTER_PREADY" \
"PSLVERR:MASTER_PSLVERR" }
save_smartdesign -sd_name ${sd_name}
generate_component -component_name ${sd_name} -recursive 0
script_support/components/CAPE.tcl 0 → 100644
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# Creating SmartDesign CAPE
set sd_name {CAPE}
create_smartdesign -sd_name ${sd_name}
#-------------------------------------------------------------------------------
# Create APB Bus
#-------------------------------------------------------------------------------
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
"APBSLOT0ENABLE:true" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:false" "APBSLOT3ENABLE:false" \
"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
"APB_DWIDTH:32" \
"IADDR_OPTION:0" \
"MADDR_BITS:28" \
"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
"SC_12:false" "SC_13:false" "SC_14:false" \
"SC_15:false" \
"UPR_NIBBLE_POSN:6"}
sd_instantiate_component -sd_name {CAPE} -component_name {CoreAPB3_CAPE} -instance_name {}
#-------------------------------------------------------------------------------
# Create APB Bus Converter
#-------------------------------------------------------------------------------
sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
#-------------------------------------------------------------------------------
# Add Default Cape GPIOs
#-------------------------------------------------------------------------------
sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_DEFAULT_GPIOS} -instance_name {CAPE_DEFAULT_GPIOS}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OUT} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OE} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_IN} -port_name {}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P9_41}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_14}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_17}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_12}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_11}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_16}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_15}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P9_15}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P9_23}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P9_12}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_26}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_18}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_7}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_8}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_10}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_9}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P9_30}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P9_27}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P9_25}
#-------------------------------------------------------------------------------
# LCD interface stub
#-------------------------------------------------------------------------------
sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_LCD} -instance_name {CAPE_LCD_STUB}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PRESETN} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PCLK} -port_name {}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA0} -new_port_name {P8_31}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA1} -new_port_name {P8_32}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA2} -new_port_name {P8_33}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA3} -new_port_name {P8_34}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA4} -new_port_name {P8_35}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA5} -new_port_name {P8_36}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA6} -new_port_name {P8_37}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA7} -new_port_name {P8_38}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA8} -new_port_name {P8_39}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA9} -new_port_name {P8_40}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA10} -new_port_name {P8_41}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA11} -new_port_name {P8_42}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA12} -new_port_name {P8_43}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA13} -new_port_name {P8_44}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA14} -new_port_name {P8_45}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA15} -new_port_name {P8_46}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_HSYNC} -new_port_name {P8_29}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_AC_BIAS} -new_port_name {P8_30}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_VSYNC} -new_port_name {P8_27}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_PCLK} -new_port_name {P8_28}
#-------------------------------------------------------------------------------
# PWM
#-------------------------------------------------------------------------------
sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_0}
sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_4} -port_name {}
sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_0} -port_name {}
sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_1} -port_name {}
sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_2} -port_name {}
sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_3} -port_name {}
sd_rename_port -sd_name {CAPE} -current_port_name {PWM_0_0} -new_port_name {P9_42}
sd_rename_port -sd_name {CAPE} -current_port_name {PWM_1} -new_port_name {P9_14}
sd_rename_port -sd_name {CAPE} -current_port_name {PWM_2} -new_port_name {P9_16}
sd_rename_port -sd_name {CAPE} -current_port_name {PWM_3} -new_port_name {P8_19}
sd_rename_port -sd_name {CAPE} -current_port_name {PWM_4} -new_port_name {P8_13}
#-------------------------------------------------------------------------------
# Connections
#-------------------------------------------------------------------------------
sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "PWM_0:PRESETN"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "PWM_0:PCLK"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_LCD_STUB:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {APB_BUS_CONVERTER_0:APB_SLAVE} -port_name {}
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster"}
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign CAPE
generate_component -component_name ${sd_name}
script_support/components/CAPE_DEFAULT_GPIOS.tcl 0 → 100644
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# Creating SmartDesign CAPE_DEFAULT_GPIOS
set sd_name {CAPE_DEFAULT_GPIOS}
create_smartdesign -sd_name ${sd_name}
# Add GPIO BIBUFs
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_16_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_17_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_18_BIBUF}
sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[0:18]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[5:5]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[6:6]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[7:7]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[8:8]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[9:9]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[10:10]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[11:11]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[12:12]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[13:13]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[14:14]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[15:15]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[16:16]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[18:18]"}
sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OE} -port_direction {IN} -port_range {[0:18]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[5:5]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[6:6]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[7:7]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[8:8]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[9:9]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[10:10]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[11:11]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[12:12]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[13:13]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[14:14]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[15:15]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[16:16]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[18:18]"}
sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[0:18]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[5:5]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[6:6]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[7:7]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[8:8]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[9:9]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[10:10]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[11:11]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[12:12]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[13:13]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[14:14]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[15:15]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[16:16]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[18:18]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:D" "GPIO_OUT[0:0]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_1_BIBUF:D" "GPIO_OUT[1:1]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_2_BIBUF:D" "GPIO_OUT[2:2]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_3_BIBUF:D" "GPIO_OUT[3:3]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_4_BIBUF:D" "GPIO_OUT[4:4]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_5_BIBUF:D" "GPIO_OUT[5:5]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:D" "GPIO_OUT[6:6]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:D" "GPIO_OUT[7:7]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:D" "GPIO_OUT[8:8]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:D" "GPIO_OUT[9:9]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_10_BIBUF:D" "GPIO_OUT[10:10]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:D" "GPIO_OUT[11:11]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:D" "GPIO_OUT[12:12]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:D" "GPIO_OUT[13:13]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:D" "GPIO_OUT[14:14]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:D" "GPIO_OUT[15:15]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_16_BIBUF:D" "GPIO_OUT[16:16]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:D" "GPIO_OUT[17:17]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:D" "GPIO_OUT[18:18]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:E" "GPIO_OE[0:0]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_1_BIBUF:E" "GPIO_OE[1:1]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_2_BIBUF:E" "GPIO_OE[2:2]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_3_BIBUF:E" "GPIO_OE[3:3]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_4_BIBUF:E" "GPIO_OE[4:4]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_5_BIBUF:E" "GPIO_OE[5:5]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:E" "GPIO_OE[6:6]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:E" "GPIO_OE[7:7]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:E" "GPIO_OE[8:8]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:E" "GPIO_OE[9:9]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_10_BIBUF:E" "GPIO_OE[10:10]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:E" "GPIO_OE[11:11]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:E" "GPIO_OE[12:12]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:E" "GPIO_OE[13:13]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:E" "GPIO_OE[14:14]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:E" "GPIO_OE[15:15]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_16_BIBUF:E" "GPIO_OE[16:16]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:E" "GPIO_OE[17:17]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:E" "GPIO_OE[18:18]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:Y" "GPIO_IN[0:0]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_1_BIBUF:Y" "GPIO_IN[1:1]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_2_BIBUF:Y" "GPIO_IN[2:2]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_3_BIBUF:Y" "GPIO_IN[3:3]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_4_BIBUF:Y" "GPIO_IN[4:4]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_5_BIBUF:Y" "GPIO_IN[5:5]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:Y" "GPIO_IN[6:6]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:Y" "GPIO_IN[7:7]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:Y" "GPIO_IN[8:8]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:Y" "GPIO_IN[9:9]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_10_BIBUF:Y" "GPIO_IN[10:10]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:Y" "GPIO_IN[11:11]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:Y" "GPIO_IN[12:12]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:Y" "GPIO_IN[13:13]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:Y" "GPIO_IN[14:14]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:Y" "GPIO_IN[15:15]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_16_BIBUF:Y" "GPIO_IN[16:16]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:Y" "GPIO_IN[17:17]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:Y" "GPIO_IN[18:18]"}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_0} -new_port_name {GPIO_1_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_1} -new_port_name {GPIO_2_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_2} -new_port_name {GPIO_3_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_3} -new_port_name {GPIO_4_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_4} -new_port_name {GPIO_5_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_5} -new_port_name {GPIO_6_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_9} -new_port_name {GPIO_10_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_10} -new_port_name {GPIO_11_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_11} -new_port_name {GPIO_12_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_12} -new_port_name {GPIO_13_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_13} -new_port_name {GPIO_14_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_14} -new_port_name {GPIO_15_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_15} -new_port_name {GPIO_16_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_16} -new_port_name {GPIO_17_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_17} -new_port_name {GPIO_18_PAD}
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign CAPE_DEFAULT_GPIOS
generate_component -component_name ${sd_name}
script_support/components/CAPE_PWM.tcl 0 → 100644
+ 75
− 0
View file @ 3acbf6dc
# Creating SmartDesign CAPE_PWM
set sd_name {CAPE_PWM}
create_smartdesign -sd_name ${sd_name}
create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -component_name {corepwm_C1} -params {\
"APB_DWIDTH:32" "CONFIG_MODE:0" \
"DAC_MODE1:false" "DAC_MODE2:false" "DAC_MODE3:false" "DAC_MODE4:false" "DAC_MODE5:false" \
"DAC_MODE6:false" "DAC_MODE7:false" "DAC_MODE8:false" "DAC_MODE9:false" "DAC_MODE10:false" \
"DAC_MODE11:false" "DAC_MODE12:false" "DAC_MODE13:false" "DAC_MODE14:false" "DAC_MODE15:false" \
"DAC_MODE16:false" \
"FIXED_PERIOD:1" "FIXED_PERIOD_EN:false" "FIXED_PRESCALE:0" "FIXED_PRESCALE_EN:false" \
"FIXED_PWM_NEGEDGE1:0" "FIXED_PWM_NEGEDGE2:0" "FIXED_PWM_NEGEDGE3:0" "FIXED_PWM_NEGEDGE4:0" "FIXED_PWM_NEGEDGE5:0" \
"FIXED_PWM_NEGEDGE6:0" "FIXED_PWM_NEGEDGE7:0" "FIXED_PWM_NEGEDGE8:0" "FIXED_PWM_NEGEDGE9:0" "FIXED_PWM_NEGEDGE10:0" \
"FIXED_PWM_NEGEDGE11:0" "FIXED_PWM_NEGEDGE12:0" "FIXED_PWM_NEGEDGE13:0" "FIXED_PWM_NEGEDGE14:0" "FIXED_PWM_NEGEDGE15:0" \
"FIXED_PWM_NEGEDGE16:0" \
"FIXED_PWM_NEG_EN1:false" "FIXED_PWM_NEG_EN2:false" "FIXED_PWM_NEG_EN3:false" "FIXED_PWM_NEG_EN4:false" "FIXED_PWM_NEG_EN5:false" \
"FIXED_PWM_NEG_EN6:false" "FIXED_PWM_NEG_EN7:false" "FIXED_PWM_NEG_EN8:false" "FIXED_PWM_NEG_EN9:false" "FIXED_PWM_NEG_EN10:false" \
"FIXED_PWM_NEG_EN11:false" "FIXED_PWM_NEG_EN12:false" "FIXED_PWM_NEG_EN13:false" "FIXED_PWM_NEG_EN14:false" "FIXED_PWM_NEG_EN15:false" \
"FIXED_PWM_NEG_EN16:false" \
"FIXED_PWM_POSEDGE1:0" "FIXED_PWM_POSEDGE2:0" "FIXED_PWM_POSEDGE3:0" "FIXED_PWM_POSEDGE4:0" "FIXED_PWM_POSEDGE5:0" \
"FIXED_PWM_POSEDGE6:0" "FIXED_PWM_POSEDGE7:0" "FIXED_PWM_POSEDGE8:0" "FIXED_PWM_POSEDGE9:0" "FIXED_PWM_POSEDGE10:0" \
"FIXED_PWM_POSEDGE11:0" "FIXED_PWM_POSEDGE12:0" "FIXED_PWM_POSEDGE13:0" "FIXED_PWM_POSEDGE14:0" "FIXED_PWM_POSEDGE15:0" \
"FIXED_PWM_POSEDGE16:0" \
"FIXED_PWM_POS_EN1:false" "FIXED_PWM_POS_EN2:false" "FIXED_PWM_POS_EN3:false" "FIXED_PWM_POS_EN4:false" "FIXED_PWM_POS_EN5:false" \
"FIXED_PWM_POS_EN6:true" "FIXED_PWM_POS_EN7:true" "FIXED_PWM_POS_EN8:true" "FIXED_PWM_POS_EN9:true" "FIXED_PWM_POS_EN10:true" \
"FIXED_PWM_POS_EN11:true" "FIXED_PWM_POS_EN12:true" "FIXED_PWM_POS_EN13:true" "FIXED_PWM_POS_EN14:true" "FIXED_PWM_POS_EN15:true" \
"FIXED_PWM_POS_EN16:true" \
"PWM_NUM:5" \
"PWM_STRETCH_VALUE1:false" "PWM_STRETCH_VALUE2:false" "PWM_STRETCH_VALUE3:false" "PWM_STRETCH_VALUE4:false" "PWM_STRETCH_VALUE5:false" \
"PWM_STRETCH_VALUE6:false" "PWM_STRETCH_VALUE7:false" "PWM_STRETCH_VALUE8:false" "PWM_STRETCH_VALUE9:false" "PWM_STRETCH_VALUE10:false" \
"PWM_STRETCH_VALUE11:false" "PWM_STRETCH_VALUE12:false" "PWM_STRETCH_VALUE13:false" "PWM_STRETCH_VALUE14:false" "PWM_STRETCH_VALUE15:false" \
"PWM_STRETCH_VALUE16:false" \
"SEPARATE_PWM_CLK:false" \
"SHADOW_REG_EN1:false" "SHADOW_REG_EN2:false" "SHADOW_REG_EN3:false" "SHADOW_REG_EN4:false" "SHADOW_REG_EN5:false" \
"SHADOW_REG_EN6:false" "SHADOW_REG_EN7:false" "SHADOW_REG_EN8:false" "SHADOW_REG_EN9:false" \
"SHADOW_REG_EN10:false" "SHADOW_REG_EN11:false" "SHADOW_REG_EN12:false" "SHADOW_REG_EN13:false" \
"SHADOW_REG_EN14:false" "SHADOW_REG_EN15:false" "SHADOW_REG_EN16:false" \
"TACHINT_ACT_LEVEL:false" \
"TACH_EDGE1:false" "TACH_EDGE2:false" "TACH_EDGE3:false" "TACH_EDGE4:false" "TACH_EDGE5:false" \
"TACH_EDGE6:false" "TACH_EDGE7:false" "TACH_EDGE8:false" "TACH_EDGE9:false" "TACH_EDGE10:false" \
"TACH_EDGE11:false" "TACH_EDGE12:false" "TACH_EDGE13:false" "TACH_EDGE14:false" "TACH_EDGE15:false" \
"TACH_EDGE16:false" \
"TACH_NUM:1"}
sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[0:0]"}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:APBslave} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PRESETN} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PCLK} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[0:0]} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[4:4]} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[3:3]} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[2:2]} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[1:1]} -port_name {}
sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_3} -new_port_name {PWM_4}
sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_2} -new_port_name {PWM_3}
sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_1} -new_port_name {PWM_2}
sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_0} -new_port_name {PWM_1}
sd_rename_port -sd_name ${sd_name} -current_port_name {PWM} -new_port_name {PWM_0}
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign CAPE_PWM
generate_component -component_name ${sd_name}
script_support/components/MPFS_ICICLE_BASE_DESIGN.tcl
+ 259
− 2
View file @ 3acbf6dc
This diff is collapsed.
script_support/components/P8_GPIO_LCD.tcl 0 → 100644
+ 241
− 0
View file @ 3acbf6dc
# Creating SmartDesign P8_GPIO_LCD
set sd_name {P8_GPIO_LCD}
create_smartdesign -sd_name ${sd_name}
# Add GPIO BIBUFs
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_0_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_1_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_2_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_3_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_4_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_5_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_6_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_7_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_8_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_9_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_10_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_11_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_12_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_13_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_14_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_15_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_16_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_17_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_18_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_HSYNC_GPIO_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_AC_BIAS_GPIO_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_VSYNC_GPIO_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_PCLK_GPIO_BIBUF}
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_LCD} -params {\
"APB_WIDTH:32" \
"FIXED_CONFIG_0:true" "FIXED_CONFIG_1:true" "FIXED_CONFIG_2:true" "FIXED_CONFIG_3:true" "FIXED_CONFIG_4:true" \
"FIXED_CONFIG_5:true" "FIXED_CONFIG_6:true" "FIXED_CONFIG_7:true" "FIXED_CONFIG_8:true" "FIXED_CONFIG_9:true" \
"FIXED_CONFIG_10:true" "FIXED_CONFIG_11:true" "FIXED_CONFIG_12:true" "FIXED_CONFIG_13:true" "FIXED_CONFIG_14:true" \
"FIXED_CONFIG_15:true" "FIXED_CONFIG_16:true" "FIXED_CONFIG_17:true" "FIXED_CONFIG_18:true" "FIXED_CONFIG_19:true" \
"FIXED_CONFIG_20:false" "FIXED_CONFIG_21:false" "FIXED_CONFIG_22:false" "FIXED_CONFIG_23:false" "FIXED_CONFIG_24:false" \
"FIXED_CONFIG_25:false" "FIXED_CONFIG_26:false" "FIXED_CONFIG_27:false" "FIXED_CONFIG_28:false" "FIXED_CONFIG_29:false" \
"FIXED_CONFIG_30:false" "FIXED_CONFIG_31:false" \
"INT_BUS:0" \
"IO_INT_TYPE_0:7" "IO_INT_TYPE_1:7" "IO_INT_TYPE_2:7" "IO_INT_TYPE_3:7" "IO_INT_TYPE_4:7" \
"IO_INT_TYPE_5:7" "IO_INT_TYPE_6:7" "IO_INT_TYPE_7:7" "IO_INT_TYPE_8:7" "IO_INT_TYPE_9:7" \
"IO_INT_TYPE_10:7" "IO_INT_TYPE_11:7" "IO_INT_TYPE_12:7" "IO_INT_TYPE_13:7" "IO_INT_TYPE_14:7" \
"IO_INT_TYPE_15:7" "IO_INT_TYPE_16:7" "IO_INT_TYPE_17:7" "IO_INT_TYPE_18:7" "IO_INT_TYPE_19:7" \
"IO_INT_TYPE_20:7" "IO_INT_TYPE_21:7" "IO_INT_TYPE_22:7" "IO_INT_TYPE_23:7" "IO_INT_TYPE_24:7" \
"IO_INT_TYPE_25:7" "IO_INT_TYPE_26:7" "IO_INT_TYPE_27:7" "IO_INT_TYPE_28:7" "IO_INT_TYPE_29:7" \
"IO_INT_TYPE_30:7" "IO_INT_TYPE_31:7" \
"IO_NUM:20" \
"IO_TYPE_0:2" "IO_TYPE_1:2" "IO_TYPE_2:2" "IO_TYPE_3:2" "IO_TYPE_4:2" "IO_TYPE_5:2" "IO_TYPE_6:2" "IO_TYPE_7:2" "IO_TYPE_8:2" "IO_TYPE_9:2" \
"IO_TYPE_10:2" "IO_TYPE_11:2" "IO_TYPE_12:2" "IO_TYPE_13:2" "IO_TYPE_14:2" "IO_TYPE_15:2" "IO_TYPE_16:2" "IO_TYPE_17:2" "IO_TYPE_18:2" "IO_TYPE_19:2" \
"IO_TYPE_20:0" "IO_TYPE_21:0" "IO_TYPE_22:0" "IO_TYPE_23:0" "IO_TYPE_24:0" "IO_TYPE_25:0" "IO_TYPE_26:0" "IO_TYPE_27:0" "IO_TYPE_28:0" "IO_TYPE_29:0" \
"IO_TYPE_30:0" "IO_TYPE_31:0" \
"IO_VAL_0:0" "IO_VAL_1:0" "IO_VAL_2:0" "IO_VAL_3:0" "IO_VAL_4:0" "IO_VAL_5:0" "IO_VAL_6:0" "IO_VAL_7:0" "IO_VAL_8:0" "IO_VAL_9:0" \
"IO_VAL_10:0" "IO_VAL_11:0" "IO_VAL_12:0" "IO_VAL_13:0" "IO_VAL_14:0" "IO_VAL_15:0" "IO_VAL_16:0" "IO_VAL_17:0" "IO_VAL_18:0" "IO_VAL_19:0" \
"IO_VAL_20:0" "IO_VAL_21:0" "IO_VAL_22:0" "IO_VAL_23:0" "IO_VAL_24:0" "IO_VAL_25:0" "IO_VAL_26:0" "IO_VAL_27:0" "IO_VAL_28:0" "IO_VAL_29:0" \
"IO_VAL_30:0" "IO_VAL_31:0" \
"OE_TYPE:0"}
sd_instantiate_component -sd_name {P8_GPIO_LCD} -component_name {CoreGPIO_LCD} -instance_name {}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[19:19]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[18:18]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[16:16]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[15:15]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[14:14]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[13:13]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[12:12]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[11:11]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[10:10]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[9:9]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[8:8]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[7:7]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[6:6]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[5:5]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[19:19]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[18:18]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[16:16]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[15:15]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[14:14]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[13:13]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[12:12]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[11:11]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[10:10]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[9:9]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[8:8]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[7:7]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[6:6]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[5:5]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[19:19]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[18:18]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[16:16]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[15:15]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[14:14]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[13:13]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[12:12]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[11:11]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[10:10]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[9:9]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[8:8]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[7:7]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[6:6]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[5:5]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[0:0]"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[0:0]" "LCD_GPIO_0_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[0:0]" "LCD_GPIO_0_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[0:0]" "LCD_GPIO_0_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[1:1]" "LCD_GPIO_1_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[1:1]" "LCD_GPIO_1_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[1:1]" "LCD_GPIO_1_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[2:2]" "LCD_GPIO_2_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[2:2]" "LCD_GPIO_2_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[2:2]" "LCD_GPIO_2_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[3:3]" "LCD_GPIO_3_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[3:3]" "LCD_GPIO_3_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[3:3]" "LCD_GPIO_3_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[4:4]" "LCD_GPIO_4_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[4:4]" "LCD_GPIO_4_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[4:4]" "LCD_GPIO_4_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[5:5]" "LCD_GPIO_5_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[5:5]" "LCD_GPIO_5_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[5:5]" "LCD_GPIO_5_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[6:6]" "LCD_GPIO_6_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[6:6]" "LCD_GPIO_6_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[6:6]" "LCD_GPIO_6_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[7:7]" "LCD_GPIO_7_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[7:7]" "LCD_GPIO_7_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[7:7]" "LCD_GPIO_7_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[8:8]" "LCD_GPIO_8_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[8:8]" "LCD_GPIO_8_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[8:8]" "LCD_GPIO_8_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[9:9]" "LCD_GPIO_9_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[9:9]" "LCD_GPIO_9_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[9:9]" "LCD_GPIO_9_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[10:10]" "LCD_GPIO_10_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[10:10]" "LCD_GPIO_10_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[10:10]" "LCD_GPIO_10_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[11:11]" "LCD_GPIO_11_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[11:11]" "LCD_GPIO_11_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[11:11]" "LCD_GPIO_11_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[12:12]" "LCD_GPIO_12_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[12:12]" "LCD_GPIO_12_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[12:12]" "LCD_GPIO_12_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[13:13]" "LCD_GPIO_13_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[13:13]" "LCD_GPIO_13_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[13:13]" "LCD_GPIO_13_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[14:14]" "LCD_GPIO_14_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[14:14]" "LCD_GPIO_14_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[14:14]" "LCD_GPIO_14_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[15:15]" "LCD_GPIO_15_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[15:15]" "LCD_GPIO_15_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[15:15]" "LCD_GPIO_15_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[16:16]" "LCD_HSYNC_GPIO_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[16:16]" "LCD_HSYNC_GPIO_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[16:16]" "LCD_HSYNC_GPIO_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[18:18]" "LCD_VSYNC_GPIO_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[18:18]" "LCD_VSYNC_GPIO_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[18:18]" "LCD_VSYNC_GPIO_BIBUF:E"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[19:19]" "LCD_PCLK_GPIO_BIBUF:D"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[19:19]" "LCD_PCLK_GPIO_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[19:19]" "LCD_PCLK_GPIO_BIBUF:E"}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD} -new_port_name {LCD_DATA0}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_0} -new_port_name {LCD_DATA1}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_1} -new_port_name {LCD_DATA2}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_2} -new_port_name {LCD_DATA3}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_3} -new_port_name {LCD_DATA4}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_4} -new_port_name {LCD_DATA5}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_5} -new_port_name {LCD_DATA6}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_6} -new_port_name {LCD_DATA7}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_7} -new_port_name {LCD_DATA8}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_8} -new_port_name {LCD_DATA9}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_9} -new_port_name {LCD_DATA10}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_10} -new_port_name {LCD_DATA11}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_11} -new_port_name {LCD_DATA12}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_12} -new_port_name {LCD_DATA13}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_13} -new_port_name {LCD_DATA14}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_14} -new_port_name {LCD_DATA15}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_15} -new_port_name {LCD_HSYNC}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_16} -new_port_name {LCD_AC_BIAS}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_17} -new_port_name {LCD_VSYNC}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_18} -new_port_name {LCD_PCLK}
sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PRESETN} -port_name {}
sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PCLK} -port_name {}
sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:APB_bif} -port_name {}
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign P8_GPIO_LCD
generate_component -component_name ${sd_name}
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