- Optimize MSS GPIO_2 usage.
- GPIOS build option now uses GPIOs for all cape pins except I2C on
  P9_PIN19 and P9_PIN20 which are hard-wired to MSS I2C.
- Move user LEDs control to MSS GPIO_2.

The TOP_LEVEL_NAME build argument allows choosing the name of the
gateware's top level name. This can be used to identify different
variants of the gateware design.

The M2_W_DISABLEx are tied low to not de-activate wifi radio.

Add SYZYGY port design option allowing loopback of all 3 SERDES lanes
and SGMII interface.
Please note this design option is mutually exclusive with the M.2
default design option. use M2_OPTION:NONE when using this design option.

This was tested using the following libero script options:
libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE CAPE_OPTION:NONE HIGH_SPEED_CONN_OPTION:BOARD_VALIDATION_SEEED_STUDIO"

Connect VIO_ENABLE control signal to MSS GPIO_2[30].

  - Temporary removal of MIPI-CSI interface.

  - Add over-current input to MSS GPIO_1 input 23.
  - Rename USB signal names to match shcematics.

  - Add PLL to generate 4.915MHz clock for ADC_MCLK.
  - Connect ADC interrupt to MSS GPIO 1 input 20.

  - Connect Ethernet management interface to PHY.
  - Connect PHY reset input to FPGA system reset.
  - Connect PHY interrupt to MSS F2M fabric interrupt 2.

  - Connected MMUART_4 to cape P9 connector pins 11 and 13.
  - Added pin constraints for cape P9 connector pins 11 and 13.

  - Move PCIe and closely associated block out of top level design into
    a new sublock containing all FPGA fabric components related to the
    M.2 interface.

  - Connect MMUART_0 to the debug header.
  - Remove the second Ethernet MAC to free up pins for MMUART_0
  - Connect MMUART_1 to the M.2 interface. Chose MMUART1 because
    RTX/CTS is avaialble on that UART.

Add place holder MIPI CSI interface for the purpose of validating board pin assignment choices.