The PROG_EXPORT_PATH script argument should eventually replace
FPE_EXPORT_PATH to specify the location of the generated programming
files whether for FlashProExpress, programming through Linux or using
DirectC.

The TOP_LEVEL_NAME build argument allows choosing the name of the
gateware's top level name. This can be used to identify different
variants of the gateware design.

- Add floor placement for CCC/PLL.
- Add FPGA fabric interfaces clock groups.
- Enable timing verification as part gateware build flow.

Add HIGH_SPEED_CONN Liberop script argument to select between no high
speed connector being included in the design (NONE) or including a
design stub (IO_STUB) exposing the pins used by the high speed
connector. The later being used to validate I/O pin constraints.

Couple the pin constraint files with the variant of design blocks.
This should allow us to customize cape I/Os to best suit a specific
cape. It also allows to easily include or excluse a block from the
design. For example, not include cape, M.2, MIPI-CSI or high speed
interface if not required and tight on FPGA resources.

  - Temporary removal of MIPI-CSI interface.

  - Removed pins reserved for probe from project options to free up
    pin C14 and C15 for use as cape pins.
  - Set pin migrations to all available devices in project settins to
    allow migration to all devices in same package.

  - Connect MMUART_0 to the debug header.
  - Remove the second Ethernet MAC to free up pins for MMUART_0
  - Connect MMUART_1 to the M.2 interface. Chose MMUART1 because
    RTX/CTS is avaialble on that UART.

Add place holder MIPI CSI interface for the purpose of validating board pin assignment choices.

Use PolarFire SoC Icicle Kit Reference Design as starting point:
  https://github.com/polarfire-soc/icicle-kit-reference-design
  hash: 4c95670cc11bd428d6bec592058f7e86b7b4fa94