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.gitlab-ci.yml
View file @ 0aa41bbc
stages: # List of stages for jobs, and their order of execution
- build
- deploy
build-job: # This job runs in the build stage, which runs first.
stage: build
tags:
- libero-soc-v2023.2
variables:
BUILD_OPTIONS_DIRECTORY: "custom-fpga-design"
BRANCH_UNDER_TEST: "develop"
rules:
- if: $CI_PIPELINE_SOURCE == "merge_request_event" && ($CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "main" || $CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "develop")
variables:
BUILD_OPTIONS_DIRECTORY: "build-options"
REPO_UNDER_TEST: $CI_MERGE_REQUEST_SOURCE_PROJECT_URL
BRANCH_UNDER_TEST: $CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
- if: $CI_PIPELINE_SOURCE == "push"
variables:
BUILD_OPTIONS_DIRECTORY: "custom-fpga-design"
REPO_UNDER_TEST: $CI_PROJECT_URL
BRANCH_UNDER_TEST: $CI_COMMIT_BRANCH
script:
- echo "Compiling the code..."
- echo "Cloning the tester and gateware..."
- export
- source ~/Microchip/Microchip-FPGA-Tools-Setup/setup-microchip-tools.sh
- git clone https://gitlab-ci-token:${CI_JOB_TOKEN}@git.beagleboard.org/beaglev-fire/gateware-builds-tester.git
- git clone https://git.beagleboard.org/beaglev-fire/gateware-builds-tester.git
- cd gateware-builds-tester
- git clone https://gitlab-ci-token:${CI_JOB_TOKEN}@git.beagleboard.org/beaglev-fire/bitstream-builder.git -b develop
- python3 bitstream-builds-tester.py ci gateware "$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME" "$CI_MERGE_REQUEST_TARGET_BRANCH_NAME"
- git clone $REPO_UNDER_TEST -b $BRANCH_UNDER_TEST
- echo "Building the gateware..."
- python3 bitstream-builds-tester.py $REPO_UNDER_TEST $BUILD_OPTIONS_DIRECTORY
- echo "$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME"
- echo "$CI_MERGE_REQUEST_TARGET_BRANCH_NAME"
- echo "Compile complete."
rules:
- if: $CI_PIPELINE_SOURCE == "merge_request_event"
when: always
artifacts:
when: always
when: on_success
paths:
- gateware-builds-tester/artifacts/tests_report.xml
- gateware-builds-tester/artifacts.zip
- gateware-builds-tester/artifacts/
- gateware-builds-tester/builds/*/work/libero/synthesis/
reports:
junit: gateware-builds-tester/artifacts/tests_report.xml
pages:
image: robertcnelson/beagle-devscripts-ubuntu-23.04-riscv64:latest
# https://git.beagleboard.org/beagleboard/ci-docker-images
stage: deploy
tags:
- docker-riscv64-ci
variables:
BUILD_OPTIONS_DIRECTORY: "custom-fpga-design"
BRANCH_UNDER_TEST: "develop"
rules:
- if: $CI_PIPELINE_SOURCE == "merge_request_event" && ($CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "main" || $CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "develop")
variables:
BUILD_OPTIONS_DIRECTORY: "build-options"
REPO_UNDER_TEST: $CI_MERGE_REQUEST_SOURCE_PROJECT_URL
BRANCH_UNDER_TEST: $CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
DEBIAN_CHANGELOG_PKG: "bbb.io-gateware"
DEBIAN_SRC: "debian"
- if: $CI_PIPELINE_SOURCE == "push"
variables:
BUILD_OPTIONS_DIRECTORY: "custom-fpga-design"
REPO_UNDER_TEST: $CI_PROJECT_URL
BRANCH_UNDER_TEST: $CI_COMMIT_BRANCH
DEBIAN_CHANGELOG_PKG: "bbb.io-gateware-my-custom-fpga-design"
DEBIAN_SRC: "debian-custom"
script:
- rm -rf ./src/ || true
- mkdir -p ./src/debian/ || true
- rsync -av ./$DEBIAN_SRC/* ./src/debian/
- mkdir -p ./src/gateware-builds-tester || true
- rsync -av ./gateware-builds-tester/* ./src/gateware-builds-tester/
- echo "$DEBIAN_CHANGELOG_PKG (1.$(LANG=C date +%Y%m%d).0-0~lunar) lunar; urgency=low" > ./src/debian/changelog
- echo "" >> ./src/debian/changelog
- echo " * ci build of $CI_PROJECT_URL" >> ./src/debian/changelog
- echo "" >> ./src/debian/changelog
- echo " -- $GITLAB_USER_NAME <$GITLAB_USER_EMAIL> $(LANG=C date -R)" >> ./src/debian/changelog
- echo "" >> ./src/debian/changelog
- cat ./src/debian/changelog
- cd ./src/ ; debuild -b -us -uc ; cd ../
- mkdir -p ./public/dists/stable/main/binary-riscv64/
- mkdir -p ./public/pool
- cp -v *.deb ./public/pool/ || true
- cp -v *.build ./public/ || true
- cp -v *.buildinfo ./public/ || true
- cd ./public ; dpkg-scanpackages ./pool/ | gzip > ./dists/stable/main/binary-riscv64/Packages.gz || true ; cd ../
- apindex public
artifacts:
when: on_success
paths:
- public
IHC_SUBSYSTEM_block_diagram.svg deleted 100644 → 0
View file @ a1ddf206
This diff is collapsed.
LICENSE 0 → 100644
View file @ 0aa41bbc
MIT License
Copyright (c) 2022 vauban353
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
README.md 0 → 100644
View file @ 0aa41bbc
# BeagleV Fire Gateware Builder
## Introduction
The BeagleV Fire gateware builder is a Python script that builds both the PolarFire SoC HSS bootloader and Libero FPGA project into a single programming bitstream. It uses a list of repositories/branches specifying the configuration of the BeagleV Fire to build.
## Prerequisites
### Python libraries
The following Python libraries are used:
- GitPython
- PyYAML
```
pip3 install gitpython
pip3 install pyyaml
```
### Microchip Tools
The SoftConsole and Libero tools from Microchip are required by the bitstream builder.
The following environment variables are required for the bitstream builder to use the Microchip tools:
- SC_INSTALL_DIR
- FPGENPROG
- LIBERO_INSTALL_DIR
- LM_LICENSE_FILE
An example script for setting up the environment is available [here](https://git.beagleboard.org/beaglev-fire/Microchip-FPGA-Tools-Setup).
## Usage
```
python3 build-bitstream.py <YAML Configuration File>
```
For example, the following command will be build the default beagleV Fire configuration:
```
python3 build-bitstream.py ./build-options/default.yaml
```
### YAML Configuration Files
The YAML configuration files are located in the "build-options" directory.
| Configuration File | Description |
| ------------------ | ---------------------------------------------------------- |
| default.yaml | Default gateware including default cape and M.2 interface. |
| minimal.yaml | Minimal Linux system including Ethernet. No FPGA gateware. |
| robotics.yaml | Similar to default but supporting the Robotics cape. |
## Supported Platforms
The BeagleV Fire gateware builder has been tested on Ubuntu 20.04.
## Microchip bitstream-builder
The BeagleV-Fire gateware builder is derived from [Microchip's bitstream-builder ](https://github.com/polarfire-soc/icicle-kit-minimal-bring-up-design-bitstream-builder). We recommend that you use either of these scripts as a starting point for your own PolarFire SoC FPGA designs as opposed to using Libero in isolation.
\ No newline at end of file
Readme.md deleted 100644 → 0
View file @ a1ddf206
# B-V-F
## Description
This repository can be used to generate a reference design for the B-V-F. This reference design will have the same or extended functionality compared to the pre-programmed FPGA design on the B-V-F.
A Libero SoC Tcl script is provided to generate the reference design using Libero SoC along with device specific I/O constraints.
This repository supports Libero SoC v2021.3, which is available for download [here](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads).
## Using the reference design generation Tcl script
```
libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE"
```
Create absolute minimal design:
```
libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE CAPE_OPTION:NONE"
```
#### Standard design generation
To generate the standard reference design which is capable of running the majority of bare metal example applications and run Linux&reg; the following flow can be used:
1. Clone or download the repository
2. Open Libero v2021.3
3. Open the execute script dialog (CTRL + U)
4. Execute the "B_V_F_REFERENCE_DESIGN.tcl" script
5. Configure the design if required
6. Run the Libero SoC design flow to program a device
## Headers
### P9
| Header Pin | FPGA Pin | Usage |
|------------|----------|------------------------------|
| 1 | n/a | DGND |
| 2 | n/a | DGND |
| 3 | n/a | VDD_3V3 |
| 4 | n/a | VDD_3V3 |
| 5 | n/a | VDD_5V |
| 6 | n/a | VDD_5V |
| 7 | n/a | SYS_5V |
| 8 | n/a | SYS_5V |
| 9 | n/a | Not connected |
| 10 | n/a | SYSRESETn |
| 11 | B5 | MMUART_4 Rx |
| 12 | C5 | MSS GPIO_2[11] (@0x20122000) |
| 13 | D19 | MMUART_4 Tx |
| 14 | C6 | PWM channel 1 (@0x41000000) |
| 15 | A5 | MSS GPIO_2[12] (@0x20122000) |
| 16 | A6 | PWM channel 2 (@0x41000000) |
| 17 | C9 | MSS GPIO_2[13] (@0x20122000) |
| 18 | C10 | MSS GPIO_2[14] (@0x20122000) |
| 19 | A11 | MSS I2C0 SCL |
| 20 | A10 | MSS I2C0 SDA |
| 21 | B8 | MSS GPIO_2[15] (@0x20122000) |
| 22 | A8 | MSS GPIO_2[16] (@0x20122000) |
| 23 | C12 | MSS GPIO_2[17] (@0x20122000) |
| 24 | B12 | MSS GPIO_2[18] (@0x20122000) |
| 25 | B7 | MSS GPIO_2[19] (@0x20122000) |
| 26 | A7 | MSS GPIO_2[20] (@0x20122000) |
| 27 | D11 | MSS GPIO_2[21] (@0x20122000) |
| 28 | C11 | MSS GPIO_2[22] (@0x20122000) |
| 29 | F17 | MSS GPIO_2[23] (@0x20122000) |
| 30 | F16 | MSS GPIO_2[24] (@0x20122000) |
| 31 | E18 | MSS GPIO_2[25] (@0x20122000) |
| 32 | n/a | VDD_ADC |
| 33 | n/a | ADC channel 4 |
| 34 | n/a | GNDA_ADC |
| 35 | n/a | ADC channel 6 |
| 36 | n/a | ADC channel 5 |
| 37 | n/a | ADC channel 2 |
| 38 | n/a | ADC channel 3 |
| 39 | n/a | ADC channel 0 |
| 40 | n/a | ADC channel 1 |
| 41 | E15 | MSS GPIO_2[26] (@0x20122000) |
| 42 | E14 | PWM channel 0 (@0x41000000) |
| 43 | n/a | GND |
| 44 | n/a | GND |
| 45 | n/a | GND |
| 46 | n/a | GND |
### P8
| Header Pin | FPGA Pin | Usage |
|------------|----------|-----------------------------------------|
| 1 | n/a | DGND |
| 2 | n/a | DGND |
| 3 | V22 | Base design FPGA GPIO[0] (@0x40000000) |
| 4 | W22 | Base design FPGA GPIO[1] (@0x40000000) |
| 5 | V19 | Base design FPGA GPIO[2] (@0x40000000) |
| 6 | V20 | Base design FPGA GPIO[3] (@0x40000000) |
| 7 | V15 | Base design FPGA GPIO[4] (@0x40000000) |
| 8 | V14 | Base design FPGA GPIO[5] (@0x40000000) |
| 9 | V21 | Base design FPGA GPIO[6] (@0x40000000) |
| 10 | W21 | Base design FPGA GPIO[7] (@0x40000000) |
| 11 | Y21 | Base design FPGA GPIO[8] (@0x40000000) |
| 12 | Y20 | Base design FPGA GPIO[9] (@0x40000000) |
| 13 | B10 | Base design FPGA GPIO[10] (@0x40000000) |
| 14 | B9 | Base design FPGA GPIO[11] (@0x40000000) |
| 15 | T12 | MSS GPIO_2[0] (@0x20122000) |
| 16 | U12 | MSS GPIO_2[1] (@0x20122000) |
| 17 | W13 | MSS GPIO_2[2] (@0x20122000) |
| 18 | T16 | MSS GPIO_2[3] (@0x20122000) |
| 19 | W18 | PWM channel 3 (@0x41000000) |
| 20 | R16 | MSS GPIO_2[4] (@0x20122000) |
| 21 | AA21 | MSS GPIO_2[5] (@0x20122000) |
| 22 | AA22 | MSS GPIO_2[6] (@0x20122000) |
| 23 | AB18 | MSS GPIO_2[7] (@0x20122000) |
| 24 | AA18 | MSS GPIO_2[8] (@0x20122000) |
| 25 | V17 | MSS GPIO_2[9] (@0x20122000) |
| 26 | A12 | MSS GPIO_2[10] (@0x20122000) |
| 27 | A13 | FPGA GPIO[18] (@0x41100000) |
| 28 | B14 | FPGA GPIO[19] (@0x41100000) |
| 29 | B13 | FPGA GPIO[16] (@0x41100000) |
| 30 | D14 | FPGA GPIO[17] (@0x41100000) |
| 31 | D13 | FPGA GPIO[0] (@0x41100000) |
| 32 | B15 | FPGA GPIO[1] (@0x41100000) |
| 33 | A15 | FPGA GPIO[2] (@0x41100000) |
| 34 | C15 | FPGA GPIO[3] (@0x41100000) |
| 35 | C14 | FPGA GPIO[4] (@0x41100000) |
| 36 | B4 | FPGA GPIO[5] (@0x41100000) |
| 37 | C4 | FPGA GPIO[6] (@0x41100000) |
| 38 | C17 | FPGA GPIO[7] (@0x41100000) |
| 39 | B17 | FPGA GPIO[8] (@0x41100000) |
| 40 | B18 | FPGA GPIO[9] (@0x41100000) |
| 41 | A18 | FPGA GPIO[10] (@0x41100000) |
| 42 | D6 | FPGA GPIO[11] (@0x41100000) |
| 43 | D7 | FPGA GPIO[12] (@0x41100000) |
| 44 | D8 | FPGA GPIO[13] (@0x41100000) |
| 45 | D9 | FPGA GPIO[14] (@0x41100000) |
| 46 | D18 | FPGA GPIO[15] (@0x41100000) |
### J9: M.2 Interface
| Header Pin | FPGA Pin | Usage |
|------------|----------|---------------------------------------------------|
| 1 | n/a | GND |
| 2 | n/a | 3.3V |
| 3 | n/a | not connected |
| 4 | n/a | 3.3V |
| 5 to 6 | n/a | not connected |
| 7 | n/a | GND |
| 8 to 17 | n/a | not connected |
| 18 | n/a | GND |
| 19 | n/a | not connected |
| 20 | R14 | M2_UART_WAKEn |
| 21 | n/a | not connected |
| 22 | T13 | M2_UART_RXD - MSS MMUART_1 through FPGA fabric |
| 24 to 31 | n/a | not connected |
| 32 | R12 | M2_UART_TXD - MSS MMUART_1 through FPGA fabric |
| 33 | n/a | GND |
| 34 | U14 | M2_UART_CTS - MSS MMUART_1 through FPGA fabric |
| 35 | F22 | M2_PET0_P |
| 36 | U13 | M2_UART_RTS - MSS MMUART_1 through FPGA fabric |
| 37 | F21 | M2_PET0_N |
| 38 | n/a | not connected |
| 39 | n/a | GND |
| 40 | n/a | not connected |
| 41 | G20 | M2_PER0_P |
| 42 | n/a | not connected |
| 43 | G19 | M2_PER0_N |
| 44 | n/a | not connected |
| 45 | n/a | GND |
| 46 | n/a | not connected |
| 47 | n/a | M2_REFCLK_P - 100MHz |
| 48 | n/a | not connected |
| 49 | n/a | M2_REFCLK_N - 100MHz |
| 50 | n/a | M2_32KHZ - connected to 32.687kHz oscillator |
| 51 | n/a | GND |
| 52 | E18 | M2_PERST0n |
| 53 | W19 | M2_CLKREQ0n |
| 54 | R15 | W _DISABLE2n - pull-up to 3.3V |
| 55 | R14 | M2_PEWAKEn |
| 56 | U19 | W _DISABLE1n - pull-up to 3.3V |
| 57 | n/a | GND |
| 58 | B1 | MSS I2C1 SDA |
| 59 | n/a | not connected |
| 60 | C1 | MSS I2C1 SCL |
| 61 | n/a | not connected |
| 62 | U15 | M2_I2C_ALTn |
| 63 | n/a | GND |
| 64 to 68 | n/a | not connected |
| 69 | n/a | GND |
| 70 to 71 | n/a | not connected |
| 72 | n/a | 3.3V |
| 73 | n/a | not connected |
| 74 | n/a | 3.3V |
| 75 | n/a | GND |
| 76 | n/a | GND |
| 77 | n/a | GND |
block_diagram.svg deleted 100644 → 0
View file @ a1ddf206
This diff is collapsed.
build-bitstream.py 0 → 100644
View file @ 0aa41bbc
# The BeagleV Fire Bitstream Builder is released under the following software license:
# Copyright 2021 Microchip Corporation.
# SPDX-License-Identifier: MIT
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to
# deal in the Software without restriction, including without limitation the
# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
# sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
# IN THE SOFTWARE.
# The BeagleV Fire Bitstream Builder is an evolution of the Microchip
# Bitstream Builder available from:
# https://github.com/polarfire-soc/icicle-kit-minimal-bring-up-design-bitstream-builder
#
import argparse
import io
import os
import platform
import shutil
import zipfile
import git
import requests
import yaml
import sys
import subprocess
import datetime
from generate_gateware_overlays import generate_gateware_overlays
def check_native_platform():
if os.path.isfile('/.dockerenv'):
return ""
else:
return " --native"
# Parse command line arguments and set tool locations
def parse_arguments():
global libero
global mss_configurator
global softconsole_headless
global programming
global update
global yaml_input_file
# Initialize parser
parser = argparse.ArgumentParser()
parser.add_argument('Path',
metavar='path',
type=str,
help='Path to the YAML file describing the list of sources used to build the bitstream.')
# Read arguments from command line
args = parser.parse_args()
yaml_input_file_arg = args.Path
if not os.path.isfile(yaml_input_file_arg):
print("\r\n!!! The path specified for the YAML input file does not exist !!!\r\n")
parser.print_help()
sys.exit()
yaml_input_file = os.path.abspath(yaml_input_file_arg)
# Tool call variables - these are the names of the tools to run which will be called from os.system.
# Full paths could be used here instead of assuming tools are in PATH
libero = "libero"
mss_configurator = "pfsoc_mss"
softconsole_headless = "softconsole-headless"
update = False
programming = False
# Checks to see if all of the required tools are installed and present in path, if a needed tool isn't available the script will exit
def check_tool_status():
if shutil.which("libero") is None:
print("Error: libero not found in path")
exit()
if shutil.which("pfsoc_mss") is None:
print("Error: polarfire soc mss configurator not found in path")
exit()
if os.environ.get('SC_INSTALL_DIR') is None:
print(
"Error: SC_INSTALL_DIR environment variable not set, please set this variable and point it to the "
"appropriate SoftConsole installation directory to run this script")
exit()
if os.environ.get('FPGENPROG') is None:
print(
"Error: FPGENPROG environment variable not set, please set this variable and point it to the appropriate "
"FPGENPROG executable to run this script")
exit()
path = os.environ["PATH"]
if "riscv-unknown-elf-gcc" not in path:
print(
"The path to the RISC-V toolchain needs to be set in PATH to run this script")
exit()
if platform.system() == "Linux" or platform.system() == "Linux2":
if shutil.which("dtc") is None:
print("Error: dtc (device-tree-compiler) not found in path")
exit()
# Creates required folders and removes artifacts before beginning
def init_workspace():
print("================================================================================")
print(" Initialize workspace")
print("================================================================================\r\n", flush=True)
# Create the sources folder to clone into if it doesn't exist (any existing source folders are handled in the
# clone_sources function)
# if not os.path.exists("./sources"):
# os.mkdir("./sources")
# Delete the work folder and its content if it exists.
if os.path.exists("./work"):
shutil.rmtree('./work')
# Create each output subdirectory
os.mkdir("./work")
os.mkdir("./work/MSS")
os.mkdir("./work/HSS")
# Delete the bitstream folder if it exists to remove previously created bitstreams.
if os.path.exists("./bitstream"):
shutil.rmtree('./bitstream')
# Create the bitstream folder structure. This is where the created bitstreams will be generated. There might be
# multiple subdirectories there to provided different programming options.
os.mkdir("./bitstream")
os.mkdir("./bitstream/FlashProExpress")
os.mkdir("./bitstream/LinuxProgramming")
print(" The FlashPro Express bitstream programming job files will be stored in")
print(" directory: ./bitstream/FlashProExpress\r\n", flush=True)
# clones the sources specified in the sources.yaml file
def clone_sources(source_list):
print("================================================================================")
print(" Clone sources")
print("================================================================================\r\n", flush=True)
source_directories = {}
with open(source_list) as f: # open the yaml file passed as an arg
data = yaml.load(f, Loader=yaml.FullLoader)
keys = data.keys()
# each entry in the file is a source
for source in keys:
# Check if this is a git source
if "git" in data.get(source).get("type"):
# Check if we've already cloned the repo
if os.path.exists(os.path.join("./sources", source)):
repo = git.Repo.init(os.path.join("./sources", source)) # set up repo
repo.git.checkout(data.get(source).get("branch")) # checkout the branch from the yaml file
repo.remotes.origin.pull() # pull changes
# We don't already have the repo, clone it
else:
repo = git.Repo.clone_from(data.get(source).get("link"), os.path.join("./sources", source),
branch=data.get(source).get("branch"))
# check if a specific commit from this branch is required
if "commit" in data.get(source):
repo.git.checkout(data.get(source).get("commit")) # check out a specific commit
# Check if this is source is a url to a zip
elif "zip" in data.get(source).get("type"):
# if we already have a source of the same name delete it - can't check versions
if os.path.exists(os.path.join("./sources", source)):
shutil.rmtree(os.path.join("./sources", source))
r = requests.get(data.get(source).get("link")) # download zip
z = zipfile.ZipFile(io.BytesIO(r.content)) # extract zip
z.extractall(os.path.join("./sources", source)) # save contents
source_directories[source] = os.path.join("./sources",
source) # Generate a dictionary of all of the sources that were cloned
f.close()
# return the dictionary of sources
return source_directories
# Calls the MSS Configurator and generate an MSS configuration in a directory based on a cfg file
def make_mss_config(mss_configurator, config_file, output_dir):
print("================================================================================")
print(" Generating MSS configuration")
print("================================================================================\r\n", flush=True)
os.system(mss_configurator + ' -GENERATE -CONFIGURATION_FILE:' + config_file + ' -OUTPUT_DIR:' + output_dir)
# Builds the HSS using a pre-defined config file using SoftConsole in headless mode
def make_hss(hss_source, yaml_input_file):
print("================================================================================")
print(" Build Hart Software Services (HSS)")
print("================================================================================\r\n", flush=True)
# Retrieve build target info from YAML file
with open(yaml_input_file) as f: # open the yaml file passed as an arg
data = yaml.load(f, Loader=yaml.FullLoader)
try:
target_board = data.get("HSS").get("board")
except:
target_board = "bvf"
f.close()
print("Target board: " + target_board)
# Update XML in HSS project
XML_file = "boards/" + target_board + "/soc_fpga_design/xml/PF_SOC_MSS_mss_cfg.xml"
XML_file_abs_path = os.path.join(hss_source, XML_file)
try:
os.remove(XML_file_abs_path)
except:
print("HSS target board does not have a default MSS XML configuration - not a problem.", flush=True)
shutil.copyfile("./work/MSS/PF_SOC_MSS_mss_cfg.xml", XML_file_abs_path)
# Select HSS configuration to build
def_config_file = os.path.join(hss_source, "boards/" + target_board + "/def_config")
shutil.copyfile(def_config_file, os.path.join(hss_source, "./.config"))
# Call HSS makefile
initial_directory = os.getcwd()
os.chdir(hss_source)
make_command = "make BOARD=" + target_board
os.system(make_command)
os.chdir(initial_directory)
# Check build was successful and copy the build artifact to the output directory
generated_hex_file = "./sources/HSS/Default/bootmode1/hss-envm-wrapper-bm1-p0.hex"
if os.path.isfile(generated_hex_file):
shutil.copyfile(generated_hex_file, "./work/HSS/hss-envm-wrapper-bm1-p0.hex")
else:
print("!!! Error: Hart Soft Service build failed !!!", flush=True)
exit()
def get_libero_script_args(source_list):
libero_script_args = "NO_BUILD_ARGUMENT"
with open(source_list) as f: # open the yaml file passed as an arg
data = yaml.load(f, Loader=yaml.FullLoader)
# try:
libero_script_args = data.get("gateware").get("build-args")
# except:
# libero_script_args = "NO_BUILD_ARGUMENT"
f.close()
if libero_script_args is None:
libero_script_args = "NONE"
return libero_script_args
#
# Retrieve/generate the gateware's design version. This version number is stored in the PolarFire SoC device and used
# as part of programming the PolarFire SoC FPGA using IAP (gateware programming from Linux).
# Care must be taken to ensure this version number is different between programming attempts. Otherwise, the PolarFire
# SoC System Controller will not attempt to program the FPGA with the new gateware if it finds the design versions are
# identical.
# The approach to managing design version numbers is to use a unique design version number for release gateware. This
# unique design version number is specified as part of the yaml build option file. The version number is dd.vv.r where
# dd identifies the design, vv is an incremental features identifier and r is a revision number.
# For development, the design version number is generated based on the gateware generation date/time. This generated
# version number loops back every 45 days given the design version number stored in PolarFire SoC is 16 bit long.
#
def get_design_version(source_list):
with open(source_list) as f: # open the yaml file passed as an arg
data = yaml.load(f, Loader=yaml.FullLoader)
unique_design_version = data.get("gateware").get("unique-design-version")
f.close()
if unique_design_version is None:
now = datetime.datetime.now()
day_of_year = now.timetuple().tm_yday
design_version = ((day_of_year %45) * 1440) + (now.hour * 60) + now.minute
else:
try:
udv_sl = unique_design_version.split(".")
design_version = (int(udv_sl[0]) * 1000) + (int(udv_sl[1]) * 10) + int(udv_sl[2])
except (ValueError, AttributeError):
print("Error: Invalid value for unique-design-version in ", source_list )
print("unique-design-version must be in the form dd.vv.r")
exit()
# FPGA design version number stored in Polarfire SoC devices is 16 bits long.
design_version = design_version % 65536
print("Design version: ", design_version)
return str(design_version)
# The function below assumes the current working directory is the gateware's git repository.
def get_git_hash():
try:
git_hash = subprocess.check_output(['git', 'log', "--pretty=format:'%H'", '-n', '1'])
except subprocess.CalledProcessError as e:
git_hash = 0
return git_hash.decode('ascii').strip("'")
# Build the gateware's top level name from the build option directory name and the git hassh of the gateware's
# repository.
def get_top_level_name():
git_hash = get_git_hash()
top_level_name = str(os.path.splitext(os.path.basename(yaml_input_file))[0])
top_level_name = top_level_name.replace('-', '_')
top_level_name = top_level_name + '_' + git_hash
if len(top_level_name) > 30:
top_level_name = top_level_name[:30]
top_level_name = top_level_name.upper()
return top_level_name
# Calls Libero and runs a script
def call_libero(libero, script, script_args, project_location, hss_image_location, prog_export_path, top_level_name, design_version):
libero_cmd = libero + " SCRIPT:" + script + " \"SCRIPT_ARGS: " + script_args + " PROJECT_LOCATION:" + project_location + " TOP_LEVEL_NAME:" + top_level_name + " HSS_IMAGE_PATH:" + hss_image_location + " PROG_EXPORT_PATH:" + prog_export_path + " DESIGN_VERSION:" + design_version + "\""
print("Libero command: " + libero_cmd, flush=True)
os.system(libero_cmd)
def generate_libero_project(libero, yaml_input_file):
print("================================================================================")
print(" Generate Libero project")
print("================================================================================\r\n", flush=True)
# Execute the Libero TCL script used to create the Libero design
initial_directory = os.getcwd()
os.chdir("./sources/FPGA-design")
project_location = os.path.join("..", "..", "work", "libero")
script = os.path.join("..", "..", "sources", "FPGA-design", "BUILD_BVF_GATEWARE.tcl")
script_args = get_libero_script_args(yaml_input_file)
design_version = get_design_version(yaml_input_file)
hss_image_location = os.path.join("..", "..", "work", "HSS", "hss-envm-wrapper-bm1-p0.hex")
prog_export_path = os.path.join("..", "..")
top_level_name = get_top_level_name()
print("top level name: ", top_level_name)
call_libero(libero, script, script_args, project_location, hss_image_location, prog_export_path, top_level_name, design_version)
os.chdir(initial_directory)
def main():
global libero
global mss_configurator
global softconsole_headless
global programming
parse_arguments()
# This function will check if all of the required tools are present and quit if they aren't
check_tool_status()
sources = {}
# Bitstream building starts here - see individual functions for a description of their purpose
init_workspace()
sources = clone_sources(yaml_input_file)
build_options_list = get_libero_script_args(yaml_input_file)
generate_gateware_overlays(os.path.join(os.getcwd(), "bitstream", "LinuxProgramming"), build_options_list)
mss_config_file_path = os.path.join(".", "sources", "MSS_Configuration", "MSS_Configuration.cfg")
work_mss_dir = os.path.join("work", "MSS")
make_mss_config(mss_configurator, mss_config_file_path, os.path.join(os.getcwd(), work_mss_dir))
make_hss(sources["HSS"], yaml_input_file)
generate_libero_project(libero, yaml_input_file)
print("Finished", flush=True)
if __name__ == '__main__':
main()
build-options/board-tests.yaml 0 → 100644
View file @ 0aa41bbc
---
HSS:
type: git
link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
type: sources
build-args: "CAPE_OPTION:GPIOS MIPI_CSI_OPTION:NONE M2_OPTION:BOARD_TESTS SYZYGY_OPTION:BOARD_TESTS_SEEED_STUDIO"
unique-design-version: 0.0.2
build-options/default.yaml 0 → 100644
View file @ 0aa41bbc
---
HSS:
type: git
link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
type: sources
unique-design-version: 2.0.2
build-options/minimal.yaml 0 → 100644
View file @ 0aa41bbc
---
HSS:
type: git
link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
type: sources
build-args: "M2_OPTION:NONE CAPE_OPTION:NONE"
unique-design-version: 1.0.2
build-options/robotics.yaml 0 → 100644
View file @ 0aa41bbc
---
HSS:
type: git
link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
type: sources
build-args: "CAPE_OPTION:ROBOTICS "
unique-design-version: 3.0.3
custom-fpga-design/my_custom_fpga_design.yaml 0 → 100644
View file @ 0aa41bbc
---
HSS:
type: git
link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
type: sources
build-args: "M2_OPTION:NONE CAPE_OPTION:SNAKEYWARE"
debian-custom/bbb.io-gateware-my-custom-fpga-design.install 0 → 100644
View file @ 0aa41bbc
gateware-builds-tester/artifacts/bitstreams/my_custom_fpga_design/DirectC/* /usr/share/beagleboard/gateware/my_custom_fpga_design/DirectC
gateware-builds-tester/artifacts/bitstreams/my_custom_fpga_design/FlashProExpress/* /usr/share/beagleboard/gateware/my_custom_fpga_design/FlashProExpress
gateware-builds-tester/artifacts/bitstreams/my_custom_fpga_design/LinuxProgramming/* /usr/share/beagleboard/gateware/my_custom_fpga_design/LinuxProgramming
\ No newline at end of file
debian-custom/changelog 0 → 100644
View file @ 0aa41bbc
bbb.io-gateware-my-custom-fpga-design (1.20231226.0-0~lunar) lunar; urgency=low
* ci build of https://git.beagleboard.org/beaglev-fire/gateware
-- Robert Nelson <robertcnelson@beagleboard.org> Tue, 26 Dec 2023 17:41:26 +0000
debian-custom/compat 0 → 100644
View file @ 0aa41bbc
10
debian-custom/control 0 → 100644
View file @ 0aa41bbc
Source: bbb.io-gateware-my-custom-fpga-design
Section: misc
Priority: extra
Maintainer: Robert Nelson <robertcnelson@gmail.com>
Build-Depends:
debhelper (>= 10)
Standards-Version: 4.5.1
Package: bbb.io-gateware-my-custom-fpga-design
Architecture: all
Depends:
${shlibs:Depends}
, ${misc:Depends}
, bbb.io-gateware
, mtd-utils
Description: bbb.io-gateware-my-custom-fpga-design
bbb.io-gateware-my-custom-fpga-design
debian-custom/rules 0 → 100755
View file @ 0aa41bbc
#!/usr/bin/make -f
# See debhelper(7) (uncomment to enable)
# output every command that modifies files on the build system.
DH_VERBOSE = 1
%:
dh $@
override_dh_builddeb:
dh_builddeb -- -Zxz
debian/bbb.io-gateware.install 0 → 100644
View file @ 0aa41bbc
debian/change-gateware.sh /usr/share/beagleboard/gateware
debian/update-gateware.sh /usr/share/microchip/gateware
debian/mcp356x_read.py /usr/share/microchip/gateware
gateware-builds-tester/artifacts/bitstreams/board-tests/DirectC/* /usr/share/beagleboard/gateware/board-tests/DirectC
gateware-builds-tester/artifacts/bitstreams/board-tests/FlashProExpress/* /usr/share/beagleboard/gateware/board-tests/FlashProExpress
gateware-builds-tester/artifacts/bitstreams/board-tests/LinuxProgramming/* /usr/share/beagleboard/gateware/board-tests/LinuxProgramming
gateware-builds-tester/artifacts/bitstreams/default/DirectC/* /usr/share/beagleboard/gateware/default/DirectC
gateware-builds-tester/artifacts/bitstreams/default/FlashProExpress/* /usr/share/beagleboard/gateware/default/FlashProExpress
gateware-builds-tester/artifacts/bitstreams/default/LinuxProgramming/* /usr/share/beagleboard/gateware/default/LinuxProgramming
gateware-builds-tester/artifacts/bitstreams/minimal/DirectC/* /usr/share/beagleboard/gateware/minimal/DirectC
gateware-builds-tester/artifacts/bitstreams/minimal/FlashProExpress/* /usr/share/beagleboard/gateware/minimal/FlashProExpress
gateware-builds-tester/artifacts/bitstreams/minimal/LinuxProgramming/* /usr/share/beagleboard/gateware/minimal/LinuxProgramming
gateware-builds-tester/artifacts/bitstreams/robotics/DirectC/* /usr/share/beagleboard/gateware/robotics/DirectC
gateware-builds-tester/artifacts/bitstreams/robotics/FlashProExpress/* /usr/share/beagleboard/gateware/robotics/FlashProExpress
gateware-builds-tester/artifacts/bitstreams/robotics/LinuxProgramming/* /usr/share/beagleboard/gateware/robotics/LinuxProgramming
debian/change-gateware.sh 0 → 100755
View file @ 0aa41bbc
#!/bin/bash
if ! id | grep -q root; then
echo "must be run as root"
exit
fi
if [ -d $1 ]
then
echo "Changing gateware."
if [ -e $1/LinuxProgramming/mpfs_bitstream.spi ]
then
if [ -e $1/LinuxProgramming/mpfs_dtbo.spi ]
then
cp -v $1/LinuxProgramming/mpfs_dtbo.spi /lib/firmware/mpfs_dtbo.spi
cp -v $1/LinuxProgramming/mpfs_bitstream.spi /lib/firmware/mpfs_bitstream.spi
sync
. /usr/share/microchip/gateware/update-gateware.sh
else
echo "No device tree overlay file found."
fi
else
echo "No gateware file found."
fi
else
echo "No directory found for this requested gateware."
fi
debian/changelog 0 → 100644
View file @ 0aa41bbc
bbb.io-gateware (1.20231226.0-0~lunar) lunar; urgency=low
* ci build of https://git.beagleboard.org/beaglev-fire/gateware
-- Robert Nelson <robertcnelson@beagleboard.org> Tue, 26 Dec 2023 17:41:26 +0000

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