MIPI-CSI: Add MIPI-CSI PHY for camera.

Camera PHY bringing camera data to cape pins for board validation
and debug.

script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl

+puts "======== Add MIPI CSI option: IMX219_PHY_TEST ========"
+
+auto_promote_pad_pins -promote_all 1
+
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/PF_IOD_GENERIC_RX_C0.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERESET_PF_C1.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERXIODBITALIGN_C1.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.tcl
+
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
+
+
+set sd_name {BVF_GATEWARE}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN34} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN35} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN37} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN38} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI1_PWND} -port_direction {OUT}
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {IMX219_IF_TOP} -instance_name {IMX219_IF_TOP_0} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[7:7]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[6:6]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[5:5]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[4:4]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[3:3]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[0:0]"} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "IMX219_IF_TOP_0:INIT_DONE"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:CAMCLK_RESET_N" "P8_PIN46"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:CAMERA_CLK" "P8_PIN45"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:FRAME_START" "P8_PIN44"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:FRAME_VALID" "P8_PIN43"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:LINE_VALID" "P8_PIN42"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:PARALLEL_CLOCK" "P8_PIN41"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[0:0]" "P8_PIN40"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[1:1]" "P8_PIN39"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[2:2]" "P8_PIN38"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[3:3]" "P8_PIN37"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[4:4]" "P8_PIN36"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[5:5]" "P8_PIN35"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[6:6]" "P8_PIN34"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[7:7]" "P8_PIN33"} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN32} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:TRNG_RST_N} -value {VCC} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CSI1_PWND} -value {VCC} 
+

script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.tcl

+# Creating SmartDesign CAM_IOD_TIP_TOP
+set sd_name {CAM_IOD_TIP_TOP}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {HS_IO_CLK_PAUSE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {HS_SEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PLL_LOCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RESTART_TRNG} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SKIP_TRNG} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRAINING_RESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_TRAIN_DONE} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_TRAIN_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L0_LP_DATA_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L0_LP_DATA} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L1_LP_DATA_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L1_LP_DATA} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L2_LP_DATA_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L2_LP_DATA} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L3_LP_DATA_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L3_LP_DATA} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {training_done_o} -port_direction {OUT}
+
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+sd_create_bus_port -sd_name ${sd_name} -port_name {RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {L0_RXD_DATA} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {L1_RXD_DATA} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {L2_RXD_DATA} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {L3_RXD_DATA} -port_direction {OUT} -port_range {[7:0]}
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add AND4_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND4} -instance_name {AND4_0}
+
+
+
+# Add CORERESET_PF_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_LOCK} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:INIT_DONE} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}
+
+
+
+# Add CORERXIODBITALIGN_C1_L0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_OOR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_HOLD} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_ERR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_EYE_IN} -value {011}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:DEM_BIT_ALGN_TAPDLY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:RX_BIT_ALIGN_LEFT_WIN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:RX_BIT_ALIGN_RGHT_WIN}
+
+
+
+# Add CORERXIODBITALIGN_C1_L1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L1}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_OOR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_HOLD} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_ERR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_EYE_IN} -value {011}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:DEM_BIT_ALGN_TAPDLY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:RX_BIT_ALIGN_LEFT_WIN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:RX_BIT_ALIGN_RGHT_WIN}
+
+
+
+# Add CORERXIODBITALIGN_C1_L2 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L2}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_OOR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_HOLD} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_ERR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_EYE_IN} -value {011}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:DEM_BIT_ALGN_TAPDLY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:RX_BIT_ALIGN_LEFT_WIN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:RX_BIT_ALIGN_RGHT_WIN}
+
+
+
+# Add CORERXIODBITALIGN_C1_L3 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L3}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_OOR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_HOLD} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_ERR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_EYE_IN} -value {011}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:DEM_BIT_ALGN_TAPDLY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:RX_BIT_ALIGN_LEFT_WIN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:RX_BIT_ALIGN_RGHT_WIN}
+
+
+
+# Add PF_IOD_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_IOD_GENERIC_RX_C0} -instance_name {PF_IOD_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[3:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_0:EYE_MONITOR_WIDTH} -value {011}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CORERESET_PF_C1_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CLK_TRAIN_DONE" "PF_IOD_0:CLK_TRAIN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CORERXIODBITALIGN_C1_L0:RESETN" "CORERXIODBITALIGN_C1_L1:RESETN" "CORERXIODBITALIGN_C1_L2:RESETN" "CORERXIODBITALIGN_C1_L3:RESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:A" "CORERXIODBITALIGN_C1_L0:BIT_ALGN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:B" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:C" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:D" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:Y" "training_done_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "PF_IOD_0:ARST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_TRAIN_ERROR" "PF_IOD_0:CLK_TRAIN_ERROR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CORERXIODBITALIGN_C1_L0:SCLK" "CORERXIODBITALIGN_C1_L1:SCLK" "CORERXIODBITALIGN_C1_L2:SCLK" "CORERXIODBITALIGN_C1_L3:SCLK" "PF_IOD_0:RX_CLK_G" "RX_CLK_G" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "TRAINING_RESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_RSTRT" "RESTART_TRNG" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_SKIP" "SKIP_TRNG" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:LP_IN" "L0_LP_DATA_N" "PF_IOD_0:L0_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:PLL_LOCK" "CORERXIODBITALIGN_C1_L1:PLL_LOCK" "CORERXIODBITALIGN_C1_L2:PLL_LOCK" "CORERXIODBITALIGN_C1_L3:PLL_LOCK" "PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:LP_IN" "L1_LP_DATA_N" "PF_IOD_0:L1_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:LP_IN" "L2_LP_DATA_N" "PF_IOD_0:L2_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:LP_IN" "L3_LP_DATA_N" "PF_IOD_0:L3_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HS_IO_CLK_PAUSE" "PF_IOD_0:HS_IO_CLK_PAUSE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HS_SEL" "PF_IOD_0:HS_SEL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L0_LP_DATA" "PF_IOD_0:L0_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L1_LP_DATA" "PF_IOD_0:L1_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L2_LP_DATA" "PF_IOD_0:L2_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L3_LP_DATA" "PF_IOD_0:L3_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RX_CLK_N" "RX_CLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RX_CLK_P" "RX_CLK_P" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L0_RXD_DATA" "PF_IOD_0:L0_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L1_RXD_DATA" "PF_IOD_0:L1_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L2_RXD_DATA" "PF_IOD_0:L2_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L3_RXD_DATA" "PF_IOD_0:L3_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RXD" "RXD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RXD_N" "RXD_N" }
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign CAM_IOD_TIP_TOP
+generate_component -component_name ${sd_name}

script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERESET_PF_C1.tcl

+# Exporting Component Description of CORERESET_PF_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component CORERESET_PF_C1
+create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C1} -params { }
+# Exporting Component Description of CORERESET_PF_C1 to TCL done

script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERXIODBITALIGN_C1.tcl

+# Exporting Component Description of CORERXIODBITALIGN_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component CORERXIODBITALIGN_C1
+create_and_configure_core -core_vlnv {Actel:DirectCore:CORERXIODBITALIGN:2.2.100} -component_name {CORERXIODBITALIGN_C1} -params {\
+"DEM_TAP_WAIT_CNT_WIDTH:3"  \
+"HOLD_TRNG:0"  \
+"MIPI_TRNG:1"  \
+"SKIP_TRNG:0"   }
+# Exporting Component Description of CORERXIODBITALIGN_C1 to TCL done

script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/PF_IOD_GENERIC_RX_C0.tcl

+# Exporting Component Description of PF_IOD_GENERIC_RX_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component PF_IOD_GENERIC_RX_C0
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.110} -component_name {PF_IOD_GENERIC_RX_C0} -params {\
+"CLOCK_DELAY_VALUE:0" \
+"DATA_RATE:500" \
+"DATA_RATIO:8" \
+"DATA_WIDTH:7" \
+"DDR_MODE:DDR" \
+"DYN_USE_WIDE_MODE:false" \
+"EXPOSE_CLK_TRAIN_PORTS:false" \
+"EXPOSE_DYNAMIC_DELAY_CTRL:false" \
+"EXPOSE_EXTRA_TRAINING_PORTS:false" \
+"EXPOSE_FA_CLK_DATA:false" \
+"EXPOSE_RX_RAW_DATA:false" \
+"FABRIC_CLK_SOURCE:GLOBAL" \
+"FRACTIONAL_CLOCK_RATIO:RATIO" \
+"ICB_BCLK_OFFSET:0" \
+"ICB_USE_WIDE_MODE:true" \
+"IO_NUMBER:4" \
+"NEED_LANECTRL:false" \
+"NEED_TIP:false" \
+"PLL_BCLK_OFFSET:3" \
+"RATIO:4" \
+"RXCTL_SPLIT_WIDTH:1" \
+"RXD_LVDS_FAILSAFE_EN:false" \
+"RXD_SPLIT_WIDTH:4" \
+"RX_BIT_SLIP_EN:false" \
+"RX_CLK_DIFFERENTIAL:true" \
+"RX_CLK_LVDS_FAILSAFE_EN:false" \
+"RX_CLK_SOURCE:HS_IO_CLK" \
+"RX_CLK_TO_DATA:DYNAMIC" \
+"RX_DATA_BUS_MODE:RX_DATA_PER_IO" \
+"RX_DATA_DIFFERENTIAL:true" \
+"RX_ENABLED:true" \
+"RX_INTERFACE_NAME:RX_DDRX_B_G_DYN" \
+"RX_IOG_ARCHETYPE:RX_DDRX_L_DYN_X4" \
+"RX_MIPI_MODE:true" \
+"SIMULATION_MODE:FULL" \
+"USE_SHARED_PLL:false" \
+"X1_ADD_DELAY_LINE_ON_CLOCK:false" }
+# Exporting Component Description of PF_IOD_GENERIC_RX_C0 to TCL done

script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl

+# Exporting Component Description of CORERESET_PF_C2 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component CORERESET_PF_C2
+create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C2} -params { }
+# Exporting Component Description of CORERESET_PF_C2 to TCL done

script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl

+# Creating SmartDesign IMX219_IF_TOP
+set sd_name {IMX219_IF_TOP}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMCLK_RESET_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {FRAME_START} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {FRAME_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LINE_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PARALLEL_CLOCK} -port_direction {OUT}
+
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_D_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_D_P} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_OUT} -port_direction {OUT} -port_range {[7:0]}
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add CORERESET_PF_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}
+
+
+
+# Add CORERESET_PF_C2_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C2} -instance_name {CORERESET_PF_C2_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:BANK_y_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:PLL_POWERDOWN_B}
+
+
+
+# Add CSI2_RXDecoder_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C0} -instance_name {CSI2_RXDecoder_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_0:DATA_O} -pin_slices {[9:2]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:FRAME_END_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_START_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_END_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:ECC_ERROR_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:CRC_ERROR_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:EBD_VALID_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:VIRTUAL_CHANNEL_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:DATA_TYPE_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:WORD_COUNT_O}
+
+
+
+# Add PF_CCC_C2_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C2} -instance_name {PF_CCC_C2_0}
+
+
+
+# Add PF_IOD_GENERIC_RX_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {PF_IOD_GENERIC_RX_C0_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_IO_CLK_PAUSE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_SEL} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:RESTART_TRNG} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:SKIP_TRNG} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_DONE}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_ERROR}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORERESET_PF_C1_0:PLL_LOCK" "CORERESET_PF_C2_0:PLL_LOCK" "PF_CCC_C2_0:PLL_LOCK_0" "PF_IOD_GENERIC_RX_C0_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_IOD_GENERIC_RX_C0_0:TRAINING_RESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMCLK_RESET_N" "CORERESET_PF_C1_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "CORERESET_PF_C2_0:CLK" "CSI2_RXDecoder_0:CAM_CLOCK_I" "PF_CCC_C2_0:REF_CLK_0" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_G" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CSI2_RXDecoder_0:PARALLEL_CLOCK_I" "PARALLEL_CLOCK" "PF_CCC_C2_0:OUT0_FABCLK_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "CORERESET_PF_C2_0:EXT_RST_N" "PF_IOD_GENERIC_RX_C0_0:training_done_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "CORERESET_PF_C2_0:INIT_DONE" "INIT_DONE" "PF_IOD_GENERIC_RX_C0_0:ARST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C2_0:FABRIC_RESET_N" "CSI2_RXDecoder_0:RESET_N_I" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_START_O" "FRAME_START" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_VALID_O" "FRAME_VALID" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:LINE_VALID_O" "LINE_VALID" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_P" "PF_IOD_GENERIC_RX_C0_0:RXD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_N" "PF_IOD_GENERIC_RX_C0_0:RXD_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[9:2]" "DATA_OUT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_RXD_DATA" }
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign IMX219_IF_TOP
+generate_component -component_name ${sd_name}

script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl

+# Exporting Component Description of PF_CCC_C2 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component PF_CCC_C2
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.220} -component_name {PF_CCC_C2} -params {\
+"DLL_CLK_0_BANKCLK_EN:false"  \
+"DLL_CLK_0_DEDICATED_EN:false"  \
+"DLL_CLK_0_FABCLK_EN:false"  \
+"DLL_CLK_1_BANKCLK_EN:false"  \
+"DLL_CLK_1_DEDICATED_EN:false"  \
+"DLL_CLK_1_FABCLK_EN:false"  \
+"DLL_CLK_P_EN:false"  \
+"DLL_CLK_P_OPTIONS_EN:false"  \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1"  \
+"DLL_CLK_REF_OPTIONS_EN:false"  \
+"DLL_CLK_S_EN:false"  \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1"  \
+"DLL_CLK_S_OPTIONS_EN:false"  \
+"DLL_DELAY4:0"  \
+"DLL_DYNAMIC_CODE_EN:false"  \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false"  \
+"DLL_EXPORT_PWRDWN:false"  \
+"DLL_FB_CLK:Primary"  \
+"DLL_FB_EN:false"  \
+"DLL_FINE_PHASE_CODE:0"  \
+"DLL_IN:133"  \
+"DLL_JITTER:0"  \
+"DLL_MODE:PHASE_REF_MODE"  \
+"DLL_ONLY_EN:false"  \
+"DLL_OUT_0:1"  \
+"DLL_OUT_1:1"  \
+"DLL_PRIM_PHASE:90"  \
+"DLL_PRIM_PHASE_CODE:0"  \
+"DLL_SEC_PHASE:90"  \
+"DLL_SEC_PHASE_CODE:0"  \
+"DLL_SELECTED_IN:Output2"  \
+"FF_REQUIRES_LOCK_EN_0:0"  \
+"GL0_0_BANKCLK_USED:false"  \
+"GL0_0_BYPASS:0"  \
+"GL0_0_BYPASS_EN:false"  \
+"GL0_0_DEDICATED_USED:false"  \
+"GL0_0_DIV:7"  \
+"GL0_0_DIVSTART:0"  \
+"GL0_0_DYNAMIC_PH:false"  \
+"GL0_0_EXPOSE_EN:false"  \
+"GL0_0_FABCLK_GATED_USED:false"  \
+"GL0_0_FABCLK_USED:true"  \
+"GL0_0_FREQ_SEL:false"  \
+"GL0_0_IS_USED:true"  \
+"GL0_0_OUT_FREQ:170"  \
+"GL0_0_PHASE_INDEX:0"  \
+"GL0_0_PHASE_SEL:false"  \
+"GL0_0_PLL_PHASE:0"  \
+"GL0_1_BANKCLK_USED:false"  \
+"GL0_1_BYPASS:0"  \
+"GL0_1_BYPASS_EN:false"  \
+"GL0_1_DEDICATED_USED:false"  \
+"GL0_1_DIV:1"  \
+"GL0_1_DIVSTART:0"  \
+"GL0_1_DYNAMIC_PH:false"  \
+"GL0_1_EXPOSE_EN:false"  \
+"GL0_1_FABCLK_USED:false"  \
+"GL0_1_FREQ_SEL:false"  \
+"GL0_1_IS_USED:true"  \
+"GL0_1_OUT_FREQ:100"  \
+"GL0_1_PHASE_INDEX:0"  \
+"GL0_1_PHASE_SEL:false"  \
+"GL0_1_PLL_PHASE:0"  \
+"GL1_0_BANKCLK_USED:false"  \
+"GL1_0_BYPASS:0"  \
+"GL1_0_BYPASS_EN:false"  \
+"GL1_0_DEDICATED_USED:false"  \
+"GL1_0_DIV:1"  \
+"GL1_0_DIVSTART:0"  \
+"GL1_0_DYNAMIC_PH:false"  \
+"GL1_0_EXPOSE_EN:false"  \
+"GL1_0_FABCLK_GATED_USED:false"  \
+"GL1_0_FABCLK_USED:true"  \
+"GL1_0_FREQ_SEL:false"  \
+"GL1_0_IS_USED:false"  \
+"GL1_0_OUT_FREQ:100"  \
+"GL1_0_PHASE_INDEX:0"  \
+"GL1_0_PHASE_SEL:false"  \
+"GL1_0_PLL_PHASE:0"  \
+"GL1_1_BANKCLK_USED:false"  \
+"GL1_1_BYPASS:0"  \
+"GL1_1_BYPASS_EN:false"  \
+"GL1_1_DEDICATED_USED:false"  \
+"GL1_1_DIV:1"  \
+"GL1_1_DIVSTART:0"  \
+"GL1_1_DYNAMIC_PH:false"  \
+"GL1_1_EXPOSE_EN:false"  \
+"GL1_1_FABCLK_USED:false"  \
+"GL1_1_FREQ_SEL:false"  \
+"GL1_1_IS_USED:false"  \
+"GL1_1_OUT_FREQ:0"  \
+"GL1_1_PHASE_INDEX:0"  \
+"GL1_1_PHASE_SEL:false"  \
+"GL1_1_PLL_PHASE:0"  \
+"GL2_0_BANKCLK_USED:false"  \
+"GL2_0_BYPASS:0"  \
+"GL2_0_BYPASS_EN:false"  \
+"GL2_0_DEDICATED_USED:false"  \
+"GL2_0_DIV:1"  \
+"GL2_0_DIVSTART:0"  \
+"GL2_0_DYNAMIC_PH:false"  \
+"GL2_0_EXPOSE_EN:false"  \
+"GL2_0_FABCLK_GATED_USED:false"  \
+"GL2_0_FABCLK_USED:true"  \
+"GL2_0_FREQ_SEL:false"  \
+"GL2_0_IS_USED:false"  \
+"GL2_0_OUT_FREQ:100"  \
+"GL2_0_PHASE_INDEX:0"  \
+"GL2_0_PHASE_SEL:false"  \
+"GL2_0_PLL_PHASE:0"  \
+"GL2_1_BANKCLK_USED:false"  \
+"GL2_1_BYPASS:0"  \
+"GL2_1_BYPASS_EN:false"  \
+"GL2_1_DEDICATED_USED:false"  \
+"GL2_1_DIV:1"  \
+"GL2_1_DIVSTART:0"  \
+"GL2_1_DYNAMIC_PH:false"  \
+"GL2_1_EXPOSE_EN:false"  \
+"GL2_1_FABCLK_USED:false"  \
+"GL2_1_FREQ_SEL:false"  \
+"GL2_1_IS_USED:false"  \
+"GL2_1_OUT_FREQ:0"  \
+"GL2_1_PHASE_INDEX:0"  \
+"GL2_1_PHASE_SEL:false"  \
+"GL2_1_PLL_PHASE:0"  \
+"GL3_0_BANKCLK_USED:false"  \
+"GL3_0_BYPASS:0"  \
+"GL3_0_BYPASS_EN:false"  \
+"GL3_0_DEDICATED_USED:false"  \
+"GL3_0_DIV:1"  \
+"GL3_0_DIVSTART:0"  \
+"GL3_0_DYNAMIC_PH:false"  \
+"GL3_0_EXPOSE_EN:false"  \
+"GL3_0_FABCLK_GATED_USED:false"  \
+"GL3_0_FABCLK_USED:true"  \
+"GL3_0_FREQ_SEL:false"  \
+"GL3_0_IS_USED:false"  \
+"GL3_0_OUT_FREQ:100"  \
+"GL3_0_PHASE_INDEX:0"  \
+"GL3_0_PHASE_SEL:false"  \
+"GL3_0_PLL_PHASE:0"  \
+"GL3_1_BANKCLK_USED:false"  \
+"GL3_1_BYPASS:0"  \
+"GL3_1_BYPASS_EN:false"  \
+"GL3_1_DEDICATED_USED:false"  \
+"GL3_1_DIV:1"  \
+"GL3_1_DIVSTART:0"  \
+"GL3_1_DYNAMIC_PH:false"  \
+"GL3_1_EXPOSE_EN:false"  \
+"GL3_1_FABCLK_USED:false"  \
+"GL3_1_FREQ_SEL:false"  \
+"GL3_1_IS_USED:false"  \
+"GL3_1_OUT_FREQ:0"  \
+"GL3_1_PHASE_INDEX:0"  \
+"GL3_1_PHASE_SEL:false"  \
+"GL3_1_PLL_PHASE:0"  \
+"PLL_ALLOW_CCC_EXT_FB:false"  \
+"PLL_BANDWIDTH_0:2"  \
+"PLL_BANDWIDTH_1:1"  \
+"PLL_BYPASS_GO_B_0:false"  \
+"PLL_BYPASS_GO_B_1:false"  \
+"PLL_BYPASS_POST_0:0"  \
+"PLL_BYPASS_POST_0_0:false"  \
+"PLL_BYPASS_POST_0_1:false"  \
+"PLL_BYPASS_POST_0_2:false"  \
+"PLL_BYPASS_POST_0_3:false"  \
+"PLL_BYPASS_POST_1:0"  \
+"PLL_BYPASS_POST_1_0:false"  \
+"PLL_BYPASS_POST_1_1:false"  \
+"PLL_BYPASS_POST_1_2:false"  \
+"PLL_BYPASS_POST_1_3:false"  \
+"PLL_BYPASS_PRE_0:0"  \
+"PLL_BYPASS_PRE_0_0:false"  \
+"PLL_BYPASS_PRE_0_1:false"  \
+"PLL_BYPASS_PRE_0_2:false"  \
+"PLL_BYPASS_PRE_0_3:false"  \
+"PLL_BYPASS_PRE_1:0"  \
+"PLL_BYPASS_PRE_1_0:false"  \
+"PLL_BYPASS_PRE_1_1:false"  \
+"PLL_BYPASS_PRE_1_2:false"  \
+"PLL_BYPASS_PRE_1_3:false"  \
+"PLL_BYPASS_SEL_0:0"  \
+"PLL_BYPASS_SEL_0_0:false"  \
+"PLL_BYPASS_SEL_0_1:false"  \
+"PLL_BYPASS_SEL_0_2:false"  \
+"PLL_BYPASS_SEL_0_3:false"  \
+"PLL_BYPASS_SEL_1:0"  \
+"PLL_BYPASS_SEL_1_0:false"  \
+"PLL_BYPASS_SEL_1_1:false"  \
+"PLL_BYPASS_SEL_1_2:false"  \
+"PLL_BYPASS_SEL_1_3:false"  \
+"PLL_DELAY_LINE_REF_FB_0:false"  \
+"PLL_DELAY_LINE_REF_FB_1:false"  \
+"PLL_DELAY_LINE_USED_0:false"  \
+"PLL_DELAY_LINE_USED_1:false"  \
+"PLL_DELAY_STEPS_0:1"  \
+"PLL_DELAY_STEPS_1:1"  \
+"PLL_DLL_CASCADED_EN:false"  \
+"PLL_DYNAMIC_CONTROL_EN_0:true"  \
+"PLL_DYNAMIC_CONTROL_EN_1:false"  \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false"  \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false"  \
+"PLL_EXPORT_PWRDWN:false"  \
+"PLL_EXT_MAX_ADDR_0:128"  \
+"PLL_EXT_MAX_ADDR_1:128"  \
+"PLL_EXT_WAVE_SEL_0:0"  \
+"PLL_EXT_WAVE_SEL_1:0"  \
+"PLL_FB_CLK_0:GL0_0"  \
+"PLL_FB_CLK_1:GL0_1"  \
+"PLL_FEEDBACK_MODE_0:Post-VCO"  \
+"PLL_FEEDBACK_MODE_1:Post-VCO"  \
+"PLL_IN_FREQ_0:62.5"  \
+"PLL_IN_FREQ_1:100"  \
+"PLL_INT_MODE_EN_0:false"  \
+"PLL_INT_MODE_EN_1:false"  \
+"PLL_LOCK_COUNT_0:0"  \
+"PLL_LOCK_COUNT_1:0"  \
+"PLL_LP_REQUIRES_LOCK_EN_0:false"  \
+"PLL_LP_REQUIRES_LOCK_EN_1:false"  \
+"PLL_PLL_CASCADED_EN:false"  \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2"  \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true"  \
+"PLL_REF_CLK_SEL_0:false"  \
+"PLL_REF_CLK_SEL_1:false"  \
+"PLL_REFDIV_0:5"  \
+"PLL_REFDIV_1:1"  \
+"PLL_SPREAD_MODE_0:false"  \
+"PLL_SPREAD_MODE_1:false"  \
+"PLL_SSM_DEPTH_0:5"  \
+"PLL_SSM_DEPTH_1:5"  \
+"PLL_SSM_DIVVAL_0:1"  \
+"PLL_SSM_DIVVAL_1:1"  \
+"PLL_SSM_FREQ_0:32"  \
+"PLL_SSM_FREQ_1:32"  \
+"PLL_SSM_RAND_PATTERN_0:2"  \
+"PLL_SSM_RAND_PATTERN_1:2"  \
+"PLL_SSMD_EN_0:false"  \
+"PLL_SSMD_EN_1:false"  \
+"PLL_SYNC_CORNER_PLL:false"  \
+"PLL_SYNC_EN:false"  \
+"PLL_VCO_MODE_0:MIN_JITTER"  \
+"PLL_VCO_MODE_1:MIN_JITTER"   }
+# Exporting Component Description of PF_CCC_C2 to TCL done

script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc

+set_io -port_name CSI1_PWND  \
+    -pin_name Y13            \
+    -fixed true              \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name CAM_C_N  \
+    -pin_name AB13         \
+    -fixed true            \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name CAM_C_P  \
+    -pin_name AA13         \
+    -fixed true            \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_N[0]}  \
+    -pin_name AB12              \
+    -fixed true                 \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_N[1]}  \
+    -pin_name W14               \
+    -fixed true                 \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_N[2]}  \
+    -pin_name AA15              \
+    -fixed true                 \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_N[3]}  \
+    -pin_name AB15              \
+    -fixed true                 \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_P[0]}  \
+    -pin_name AA12              \
+    -fixed true                 \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_P[1]}  \
+    -pin_name Y14               \
+    -fixed true                 \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_P[2]}  \
+    -pin_name Y15               \
+    -fixed true                 \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_P[3]}  \
+    -pin_name AB14              \
+    -fixed true                 \
+    -DIRECTION OUTPUT
+
+
+
+set_io -port_name P8_PIN32	\
+    -pin_name B15	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN33	\
+    -pin_name A15	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN34	\
+    -pin_name C15	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN35	\
+    -pin_name C14	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN36	\
+    -pin_name B4	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN37	\
+    -pin_name C4	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN38	\
+    -pin_name C17	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN39	\
+    -pin_name B17	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN40	\
+    -pin_name B18	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN41	\
+    -pin_name A18	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN42	\
+    -pin_name D6	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN43	\
+    -pin_name D7	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN44	\
+    -pin_name D8	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN45	\
+    -pin_name D9	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN46	\
+    -pin_name D18	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+	

script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl

+# Exporting Component Description of mipicsi2rxdecoderPF_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component mipicsi2rxdecoderPF_C0
+create_and_configure_core -core_vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -component_name {mipicsi2rxdecoderPF_C0} -params {\
+"g_DATAWIDTH:10"  \
+"g_FIFO_SIZE:12"  \
+"g_FORMAT:0"  \
+"g_INPUT_DATA_INVERT:0"  \
+"g_LANE_WIDTH:4"  \
+"g_NUM_OF_PIXELS:1"   }
+# Exporting Component Description of mipicsi2rxdecoderPF_C0 to TCL done