Forum | Documentation | Website | Blog

Skip to content
Snippets Groups Projects
Commit e14cdd10 authored by Vauban's avatar Vauban
Browse files

MIPI_CSI: Add GPIO to read status for board tests.

parent dadeb78e
No related merge requests found
Hide whitespace changes
Inline Side-by-side
script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
+ 12
− 38
View file @ e14cdd10
......@@ -10,56 +10,30 @@ source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IO
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CoreGPIO_MIPI_CSI.tcl
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
set sd_name ${top_level_name}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN34} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN35} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN37} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN38} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI1_PWND} -port_direction {OUT}
sd_instantiate_component -sd_name ${sd_name} -component_name {IMX219_IF_TOP} -instance_name {IMX219_IF_TOP_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[7:7]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[6:6]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[5:5]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[0:0]"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "IMX219_IF_TOP_0:INIT_DONE"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:CAMCLK_RESET_N" "P8_PIN46"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:CAMERA_CLK" "P8_PIN45"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:FRAME_START" "P8_PIN44"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:FRAME_VALID" "P8_PIN43"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:LINE_VALID" "P8_PIN42"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:PARALLEL_CLOCK" "P8_PIN41"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[0:0]" "P8_PIN40"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[1:1]" "P8_PIN39"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[2:2]" "P8_PIN38"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[3:3]" "P8_PIN37"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[4:4]" "P8_PIN36"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[5:5]" "P8_PIN35"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[6:6]" "P8_PIN34"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[7:7]" "P8_PIN33"}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CSI1_PWND} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN32} -value {GND}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "IMX219_IF_TOP_0:PCLK"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "IMX219_IF_TOP_0:PRESETN"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:CSI_APB_MTARGET" "IMX219_IF_TOP_0:APB_TARGET"}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:CAMCLK_RESET_N}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:CAMERA_CLK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:FRAME_START}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:FRAME_VALID}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:LINE_VALID}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:PARALLEL_CLOCK}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:TRNG_RST_N} -value {VCC}
script_support/components/MIPI_CSI/IMX219_PHY_TEST/CoreGPIO_MIPI_CSI.tcl 0 → 100644
+ 138
− 0
View file @ e14cdd10
# Exporting Component Description of CoreGPIO_MIPI_CSI to TCL
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484E
# Create and Configure the core component CoreGPIO_MIPI_CSI
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_MIPI_CSI} -params {\
"APB_WIDTH:32" \
"FIXED_CONFIG_0:true" \
"FIXED_CONFIG_1:true" \
"FIXED_CONFIG_2:true" \
"FIXED_CONFIG_3:true" \
"FIXED_CONFIG_4:true" \
"FIXED_CONFIG_5:true" \
"FIXED_CONFIG_6:true" \
"FIXED_CONFIG_7:true" \
"FIXED_CONFIG_8:true" \
"FIXED_CONFIG_9:true" \
"FIXED_CONFIG_10:true" \
"FIXED_CONFIG_11:false" \
"FIXED_CONFIG_12:false" \
"FIXED_CONFIG_13:false" \
"FIXED_CONFIG_14:false" \
"FIXED_CONFIG_15:false" \
"FIXED_CONFIG_16:false" \
"FIXED_CONFIG_17:false" \
"FIXED_CONFIG_18:false" \
"FIXED_CONFIG_19:false" \
"FIXED_CONFIG_20:false" \
"FIXED_CONFIG_21:false" \
"FIXED_CONFIG_22:false" \
"FIXED_CONFIG_23:false" \
"FIXED_CONFIG_24:false" \
"FIXED_CONFIG_25:false" \
"FIXED_CONFIG_26:false" \
"FIXED_CONFIG_27:false" \
"FIXED_CONFIG_28:false" \
"FIXED_CONFIG_29:false" \
"FIXED_CONFIG_30:false" \
"FIXED_CONFIG_31:false" \
"INT_BUS:0" \
"IO_INT_TYPE_0:7" \
"IO_INT_TYPE_1:7" \
"IO_INT_TYPE_2:7" \
"IO_INT_TYPE_3:7" \
"IO_INT_TYPE_4:7" \
"IO_INT_TYPE_5:7" \
"IO_INT_TYPE_6:7" \
"IO_INT_TYPE_7:7" \
"IO_INT_TYPE_8:7" \
"IO_INT_TYPE_9:7" \
"IO_INT_TYPE_10:7" \
"IO_INT_TYPE_11:7" \
"IO_INT_TYPE_12:7" \
"IO_INT_TYPE_13:7" \
"IO_INT_TYPE_14:7" \
"IO_INT_TYPE_15:7" \
"IO_INT_TYPE_16:7" \
"IO_INT_TYPE_17:7" \
"IO_INT_TYPE_18:7" \
"IO_INT_TYPE_19:7" \
"IO_INT_TYPE_20:7" \
"IO_INT_TYPE_21:7" \
"IO_INT_TYPE_22:7" \
"IO_INT_TYPE_23:7" \
"IO_INT_TYPE_24:7" \
"IO_INT_TYPE_25:7" \
"IO_INT_TYPE_26:7" \
"IO_INT_TYPE_27:7" \
"IO_INT_TYPE_28:7" \
"IO_INT_TYPE_29:7" \
"IO_INT_TYPE_30:7" \
"IO_INT_TYPE_31:7" \
"IO_NUM:11" \
"IO_TYPE_0:0" \
"IO_TYPE_1:0" \
"IO_TYPE_2:0" \
"IO_TYPE_3:0" \
"IO_TYPE_4:0" \
"IO_TYPE_5:0" \
"IO_TYPE_6:0" \
"IO_TYPE_7:0" \
"IO_TYPE_8:0" \
"IO_TYPE_9:0" \
"IO_TYPE_10:0" \
"IO_TYPE_11:0" \
"IO_TYPE_12:0" \
"IO_TYPE_13:0" \
"IO_TYPE_14:0" \
"IO_TYPE_15:0" \
"IO_TYPE_16:0" \
"IO_TYPE_17:0" \
"IO_TYPE_18:0" \
"IO_TYPE_19:0" \
"IO_TYPE_20:0" \
"IO_TYPE_21:0" \
"IO_TYPE_22:0" \
"IO_TYPE_23:0" \
"IO_TYPE_24:0" \
"IO_TYPE_25:0" \
"IO_TYPE_26:0" \
"IO_TYPE_27:0" \
"IO_TYPE_28:0" \
"IO_TYPE_29:0" \
"IO_TYPE_30:0" \
"IO_TYPE_31:0" \
"IO_VAL_0:0" \
"IO_VAL_1:0" \
"IO_VAL_2:0" \
"IO_VAL_3:0" \
"IO_VAL_4:0" \
"IO_VAL_5:0" \
"IO_VAL_6:0" \
"IO_VAL_7:0" \
"IO_VAL_8:0" \
"IO_VAL_9:0" \
"IO_VAL_10:0" \
"IO_VAL_11:0" \
"IO_VAL_12:0" \
"IO_VAL_13:0" \
"IO_VAL_14:0" \
"IO_VAL_15:0" \
"IO_VAL_16:0" \
"IO_VAL_17:0" \
"IO_VAL_18:0" \
"IO_VAL_19:0" \
"IO_VAL_20:0" \
"IO_VAL_21:0" \
"IO_VAL_22:0" \
"IO_VAL_23:0" \
"IO_VAL_24:0" \
"IO_VAL_25:0" \
"IO_VAL_26:0" \
"IO_VAL_27:0" \
"IO_VAL_28:0" \
"IO_VAL_29:0" \
"IO_VAL_30:0" \
"IO_VAL_31:0" \
"OE_TYPE:0" }
# Exporting Component Description of CoreGPIO_MIPI_CSI to TCL done
script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
+ 58
− 8
View file @ e14cdd10
......@@ -6,11 +6,18 @@ create_smartdesign -sd_name ${sd_name}
auto_promote_pad_pins -promote_all 0
# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PENABLE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSEL} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PWRITE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSLVERR} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMCLK_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FRAME_START} -port_direction {OUT}
......@@ -20,17 +27,57 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {PARALLEL_CLOCK} -port_dire
# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PADDR} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PWDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_D_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_D_P} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_OUT} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PRDATA} -port_direction {OUT} -port_range {[31:0]}
# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {APB_TARGET} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"PADDR:APB_TARGET_PADDR" \
"PSELx:APB_TARGET_PSEL" \
"PENABLE:APB_TARGET_PENABLE" \
"PWRITE:APB_TARGET_PWRITE" \
"PRDATA:APB_TARGET_PRDATA" \
"PWDATA:APB_TARGET_PWDATA" \
"PREADY:APB_TARGET_PREADY" \
"PSLVERR:APB_TARGET_PSLVERR" }
# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
# Add CoreGPIO_MIPI_CSI_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_MIPI_CSI} -instance_name {CoreGPIO_MIPI_CSI_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[10:10]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[10:10]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[3:3]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[3:3]} -value {VCC}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[4:4]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[4:4]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[5:5]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[5:5]} -value {VCC}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[6:6]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[6:6]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[7:7]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[7:7]} -value {VCC}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[8:8]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[8:8]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[9:9]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[9:9]} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_OUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_OE}
# Add CORERESET_PF_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
......@@ -88,16 +135,16 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_T
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORERESET_PF_C1_0:PLL_LOCK" "CORERESET_PF_C2_0:PLL_LOCK" "PF_CCC_C2_0:PLL_LOCK_0" "PF_IOD_GENERIC_RX_C0_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_IOD_GENERIC_RX_C0_0:TRAINING_RESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMCLK_RESET_N" "CORERESET_PF_C1_0:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "CORERESET_PF_C2_0:CLK" "CSI2_RXDecoder_0:CAM_CLOCK_I" "PF_CCC_C2_0:REF_CLK_0" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_G" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CSI2_RXDecoder_0:PARALLEL_CLOCK_I" "PARALLEL_CLOCK" "PF_CCC_C2_0:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "CORERESET_PF_C2_0:EXT_RST_N" "PF_IOD_GENERIC_RX_C0_0:training_done_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "CORERESET_PF_C2_0:INIT_DONE" "INIT_DONE" "PF_IOD_GENERIC_RX_C0_0:ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C2_0:FABRIC_RESET_N" "CSI2_RXDecoder_0:RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_START_O" "FRAME_START" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_VALID_O" "FRAME_VALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_START_O" "CoreGPIO_MIPI_CSI_0:GPIO_IN[1:1]" "FRAME_START" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_VALID_O" "CoreGPIO_MIPI_CSI_0:GPIO_IN[0:0]" "FRAME_VALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA" }
......@@ -106,17 +153,20 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_I"
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:LINE_VALID_O" "LINE_VALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:LINE_VALID_O" "CoreGPIO_MIPI_CSI_0:GPIO_IN[2:2]" "LINE_VALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_MIPI_CSI_0:PCLK" "PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_MIPI_CSI_0:PRESETN" "PRESETN" }
# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_P" "PF_IOD_GENERIC_RX_C0_0:RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_N" "PF_IOD_GENERIC_RX_C0_0:RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[9:2]" "DATA_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_P" "PF_IOD_GENERIC_RX_C0_0:RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_RXD_DATA" }
# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_TARGET" "CoreGPIO_MIPI_CSI_0:APB_bif" }
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
......
script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
+ 0
− 93
View file @ e14cdd10
......@@ -62,96 +62,3 @@ set_io -port_name {CAM_D_P[3]} \
-pin_name AB14 \
-fixed true \
-DIRECTION OUTPUT
set_io -port_name P8_PIN32 \
-pin_name B15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN33 \
-pin_name A15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN34 \
-pin_name C15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN35 \
-pin_name C14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN36 \
-pin_name B4 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN37 \
-pin_name C4 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN38 \
-pin_name C17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN39 \
-pin_name B17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN40 \
-pin_name B18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN41 \
-pin_name A18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN42 \
-pin_name D6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN43 \
-pin_name D7 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN44 \
-pin_name D8 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN45 \
-pin_name D9 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P8_PIN46 \
-pin_name D18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment

Open hardware computers for makers, educators and professionals