- Temporary removal of MIPI-CSI interface.

  - Add over-current input to MSS GPIO_1 input 23.
  - Rename USB signal names to match shcematics.

  - Add PLL to generate 4.915MHz clock for ADC_MCLK.
  - Connect ADC interrupt to MSS GPIO 1 input 20.

  - Connect Ethernet management interface to PHY.
  - Connect PHY reset input to FPGA system reset.
  - Connect PHY interrupt to MSS F2M fabric interrupt 2.

  - Connected MMUART_4 to cape P9 connector pins 11 and 13.
  - Added pin constraints for cape P9 connector pins 11 and 13.

  - Move PCIe and closely associated block out of top level design into
    a new sublock containing all FPGA fabric components related to the
    M.2 interface.

  - Connect MMUART_0 to the debug header.
  - Remove the second Ethernet MAC to free up pins for MMUART_0
  - Connect MMUART_1 to the M.2 interface. Chose MMUART1 because
    RTX/CTS is avaialble on that UART.

Add place holder MIPI CSI interface for the purpose of validating board pin assignment choices.

Use PolarFire SoC Icicle Kit Reference Design as starting point:
  https://github.com/polarfire-soc/icicle-kit-reference-design
  hash: 4c95670cc11bd428d6bec592058f7e86b7b4fa94