- Adjust DDR memory layout to match the Icicle Kit's 2022.02 release
    (move to 64-bit address range).

  - Temporary removal of MIPI-CSI interface.

  - Add over-current input to MSS GPIO_1 input 23.
  - Rename USB signal names to match shcematics.

  - Add details of pins usage.
  - List all FPGA pin assignments to headers P8 and P9.

  - Add PLL to generate 4.915MHz clock for ADC_MCLK.
  - Connect ADC interrupt to MSS GPIO 1 input 20.

  - Connect Ethernet management interface to PHY.
  - Connect PHY reset input to FPGA system reset.
  - Connect PHY interrupt to MSS F2M fabric interrupt 2.

  - Removed pins reserved for probe from project options to free up
    pin C14 and C15 for use as cape pins.
  - Set pin migrations to all available devices in project settins to
    allow migration to all devices in same package.

  - Connected MMUART_4 to cape P9 connector pins 11 and 13.
  - Added pin constraints for cape P9 connector pins 11 and 13.

  - Marked pins not available in the MPFS025-FCVG484 package.
  - Identified available pins not currently used in the design.
  - Identified pins used in the design that need to be properly
    document (marked as GPIO?).

  - Move PCIe and closely associated block out of top level design into
    a new sublock containing all FPGA fabric components related to the
    M.2 interface.

  - Connect MMUART_0 to the debug header.
  - Remove the second Ethernet MAC to free up pins for MMUART_0
  - Connect MMUART_1 to the M.2 interface. Chose MMUART1 because
    RTX/CTS is avaialble on that UART.

Comment out pins from original design which are not available on
FCVG484_Eval package of the MPFS025 die.

Add place holder MIPI CSI interface for the purpose of validating board pin assignment choices.

Cleared up README from information regarding the base reference design
used as a starting point.

Use PolarFire SoC Icicle Kit Reference Design as starting point:
  https://github.com/polarfire-soc/icicle-kit-reference-design
  hash: 4c95670cc11bd428d6bec592058f7e86b7b4fa94