- All FPGA AXI bus clocks aet to 125MHz.
- FPGA APB bus clock set to 50MHz.

Add SYZYGY port design option allowing loopback of all 3 SERDES lanes
and SGMII interface.
Please note this design option is mutually exclusive with the M.2
default design option. use M2_OPTION:NONE when using this design option.

This was tested using the following libero script options:
libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE CAPE_OPTION:NONE HIGH_SPEED_CONN_OPTION:BOARD_VALIDATION_SEEED_STUDIO"

This uses the Opal Kelly SYZYGY loopback test board.

Generate PWM signals on HSIO pins to check board connectivity.

Add the IO_BOARD_VALIDATION option to the MIPI_CSI_OPION build options.

This option generates PWM signals on the MIPI CSI interface to check
board connectivity. The PWM signals have a different increasing duty
cycle from data to clock to control signasls on the interface.

Please note this requires manual Verilog source code changes to CorePWM.
file: components/Actel/DirectCore/corepwm/4.5.100/rtl/vlog/core/reg_if.v
Lines 99 and 100 nedd to  be changed as follows:
  from:
         psh_enable_reg1  <= 0;
         psh_enable_reg2  <= 0;

  to:
         psh_enable_reg1  <= 8'b11111111;
         psh_enable_reg2  <= 8'b11111111;

Connect VIO_ENABLE control signal to MSS GPIO_2[30].

Changed APB bus address decoding as follows:
 - CorePWM:  base address 0x41000000
 - CoreGPIO: base address 0x41100000