- Mar 06, 2022
- Mar 05, 2022
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Vauban authored
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- Feb 27, 2022
- Feb 21, 2022
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Vauban authored
- Connect Ethernet management interface to PHY. - Connect PHY reset input to FPGA system reset. - Connect PHY interrupt to MSS F2M fabric interrupt 2.
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- Feb 20, 2022
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Vauban authored
- Removed pins reserved for probe from project options to free up pin C14 and C15 for use as cape pins. - Set pin migrations to all available devices in project settins to allow migration to all devices in same package.
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Vauban authored
- Connected MMUART_4 to cape P9 connector pins 11 and 13. - Added pin constraints for cape P9 connector pins 11 and 13.
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- Feb 18, 2022
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Vauban authored
- Marked pins not available in the MPFS025-FCVG484 package. - Identified available pins not currently used in the design. - Identified pins used in the design that need to be properly document (marked as GPIO?).
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- Feb 14, 2022
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Vauban authored
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- Feb 13, 2022
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Vauban authored
- Move PCIe and closely associated block out of top level design into a new sublock containing all FPGA fabric components related to the M.2 interface.
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- Feb 12, 2022
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Vauban authored
- Connect MMUART_0 to the debug header. - Remove the second Ethernet MAC to free up pins for MMUART_0 - Connect MMUART_1 to the M.2 interface. Chose MMUART1 because RTX/CTS is avaialble on that UART.
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- Feb 11, 2022
- Feb 09, 2022
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Vauban authored
Add place holder MIPI CSI interface for the purpose of validating board pin assignment choices.
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Vauban authored
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Vauban authored
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Vauban authored
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Vauban authored
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Vauban authored
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Vauban authored
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Vauban authored
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Vauban authored
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Vauban authored
Cleared up README from information regarding the base reference design used as a starting point.
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Vauban authored
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Vauban authored
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Vauban authored
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Vauban authored
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- Feb 08, 2022
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Vauban authored
Use PolarFire SoC Icicle Kit Reference Design as starting point: https://github.com/polarfire-soc/icicle-kit-reference-design hash: 4c95670cc11bd428d6bec592058f7e86b7b4fa94
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