- Jul 20, 2023
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Vauban authored
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- Jul 16, 2023
- Jul 01, 2023
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Vauban authored
The PROG_EXPORT_PATH script argument should eventually replace FPE_EXPORT_PATH to specify the location of the generated programming files whether for FlashProExpress, programming through Linux or using DirectC.
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- Jun 11, 2023
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Vauban authored
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- Jun 09, 2023
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Vauban authored
Use the gateware's top level name to name the FlashPro Express job files to ease identification of gateware variants.
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Vauban authored
The TOP_LEVEL_NAME build argument allows choosing the name of the gateware's top level name. This can be used to identify different variants of the gateware design.
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- Jun 04, 2023
- May 30, 2023
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Vauban authored
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- May 24, 2023
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Vauban authored
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- May 23, 2023
- May 14, 2023
- May 13, 2023
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Vauban authored
- Clear confusionabout interrupt signal polarity by removing _N from PCIe interrupt signal name. - Tie MSS PCIe interrupt signal to ground when PCIe block not instantiated.
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- May 01, 2023
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Vauban authored
- Match changes in PCIe and DDR memory layout for non-coherent DMA transfers across the FPGA fabric.
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- Apr 29, 2023
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Vauban authored
- Add floor placement for CCC/PLL. - Add FPGA fabric interfaces clock groups. - Enable timing verification as part gateware build flow.
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- Apr 02, 2023
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Vauban authored
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- Mar 25, 2023
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Vauban authored
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- Jan 29, 2023
- Jan 15, 2023
- Dec 31, 2022
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Vauban authored
Add SYZYGY port design option allowing loopback of all 3 SERDES lanes and SGMII interface. Please note this design option is mutually exclusive with the M.2 default design option. use M2_OPTION:NONE when using this design option. This was tested using the following libero script options: libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE CAPE_OPTION:NONE HIGH_SPEED_CONN_OPTION:BOARD_VALIDATION_SEEED_STUDIO"
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Vauban authored
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- Dec 28, 2022
- Nov 27, 2022
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Vauban authored
Generate PWM signals on HSIO pins to check board connectivity.
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- Nov 20, 2022
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Vauban authored
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Vauban authored
Add the IO_BOARD_VALIDATION option to the MIPI_CSI_OPION build options. This option generates PWM signals on the MIPI CSI interface to check board connectivity. The PWM signals have a different increasing duty cycle from data to clock to control signasls on the interface. Please note this requires manual Verilog source code changes to CorePWM. file: components/Actel/DirectCore/corepwm/4.5.100/rtl/vlog/core/reg_if.v Lines 99 and 100 nedd to be changed as follows: from: psh_enable_reg1 <= 0; psh_enable_reg2 <= 0; to: psh_enable_reg1 <= 8'b11111111; psh_enable_reg2 <= 8'b11111111;
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Vauban authored
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