- Move PCIe and closely associated block out of top level design into
    a new sublock containing all FPGA fabric components related to the
    M.2 interface.

  - Connect MMUART_0 to the debug header.
  - Remove the second Ethernet MAC to free up pins for MMUART_0
  - Connect MMUART_1 to the M.2 interface. Chose MMUART1 because
    RTX/CTS is avaialble on that UART.

Comment out pins from original design which are not available on
FCVG484_Eval package of the MPFS025 die.

Add place holder MIPI CSI interface for the purpose of validating board pin assignment choices.

Cleared up README from information regarding the base reference design
used as a starting point.

Use PolarFire SoC Icicle Kit Reference Design as starting point:
  https://github.com/polarfire-soc/icicle-kit-reference-design
  hash: 4c95670cc11bd428d6bec592058f7e86b7b4fa94