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- RapidRoger18 authored
@@ -17,6 +17,7 @@ Summary links
@@ -48,29 +49,33 @@ Project
To provide the capability of a Programmable Real-time Unit Industrial Control SubSystem (PRU-ICSS), which is present on several BeagleBone boards, I propose to deploy an existing RISC-V 32IM core with a customized Instruction Set Architecture on FPGA Fabric present on BeagleV-Fire. The goal of this deployment is to provide high bandwidth between the CPU and I/O, resulting in a on-board microcontroller.
To provide the capability of a Programmable Real-time Unit Industrial Control SubSystem (PRU-ICSS), which is present on several BeagleBone boards, I propose to deploy an existing RISC-V 32IM core with a customized Instruction Set on FPGA Fabric present on BeagleV-Fire. The goal of this deployment is to provide high bandwidth between the CPU and I/O, resulting in a on-board microcontroller.
The ultimate aim of this project is to have a functional Risc-V soft core on the BeagleV-Fire FPGA fabric, which will be functionally equivalent to a PRU subsystem on the BeagleBone Black. Together with ultra-low latency I/O operations, this core will be able to execute Risc-V instructions acting as a microcontroller. BeagleV-Fire will feature a functional PRU-comparable subsystem on its FPGA fabric by the project's conclusion.
The programmable nature of the PRU, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the system-on-chip (SoC).
The main aim of this project is to deploy a soft core subsystem on BeagleV-Fire’s FPGA fabric, functionally equivalent to PRU subsystem on BeagleBone Black. The core will feature RISC-V ISA customised to perform ultra low-latency I/O operations, i.e., single-cycle execution. This deployment will provide high-bandwidth data transfer in main CPU and I/O and also ensure high speed data processing similar to a microcontroller.
The programmable nature of the PRU, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time responses, specialised data handling operations, custom peripheral interfaces, and in offloading tasks from the main processor cores of the system-on-chip (SoC).
Based on the requirements of the project, it is most efficient to use PicoRV (an open source RISC-V based processor) as a base and modify it to perform high speed I/O operations. The PicoRV possesses excellent compiler support and diverse instruction set but lacks I/O support and single-cycle execution for some instructions.
This problem will be resolved within the first stage of the project, which will focus on making the core I/O compatible and modifying its execution flow to ensure single-cycle execution for all instructions. Some present soft processor IPs like AMD’s Microblaze used in Vivado Design Suite and Microchip’s Mi-V used in Libero Design suite can provide good insights on how a functioning soft core IP will look like.
riscv64-unknown-elf-gcc compiler will compile the C program into bare-metal RISC-V based binary instructions within the linux booted on the main CPU. The communication between main CPU and PRU will be used to send these instructions into the program memory of PRU without needing to flash the FPGA each time.
@@ -150,37 +155,36 @@ Coding begins (May 27th)
@@ -192,31 +196,31 @@ Submit midterm evaluations (July 8th)
@@ -274,8 +278,7 @@ Contingency