[Minor Changes]: Adds links to repositories and update threads

This PR adds the links to update forum threads, code-in and upstream repositories to the proposal.

proposals/RISC-V_CPU_core_in_FPGA_fabric.rst

@@ -17,6 +17,7 @@ Summary links
 - - *Upstream Repository:* `BeagleV-Fire gateware <https://openbeagle.org/beaglev-fire/gateware>`_
 - - *Daily Code Check-in Repository:* `Fork for BeagleV-Fire gateware <https://openbeagle.org/Roger18/gateware>`_
 - **Weekly/biweekly Updates Forums Thread:** `Progress Reports <https://forum.beagleboard.org/t/weekly-progress-report-low-latency-i-o-risc-v-cpu-core-in-fpga-fabric/38488>`_
+
 Status
 =======
 
@@ -48,29 +49,33 @@ Project
 
 Description
 ============
-To provide the capability of a Programmable Real-time Unit Industrial Control SubSystem (PRU-ICSS), which is present on several BeagleBone boards, I propose to deploy an existing RISC-V 32IM core with a customized Instruction Set Architecture on FPGA Fabric present on BeagleV-Fire. The goal of this deployment is to provide high bandwidth between the CPU and I/O, resulting in a on-board microcontroller.
+To provide the capability of a Programmable Real-time Unit Industrial Control SubSystem (PRU-ICSS), which is present on several BeagleBone boards, I propose to deploy an existing RISC-V 32IM core with a customized Instruction Set on FPGA Fabric present on BeagleV-Fire. The goal of this deployment is to provide high bandwidth between the CPU and I/O, resulting in a on-board microcontroller.
 
 Goals and Objectives
 ====================
-The ultimate aim of this project is to have a functional Risc-V soft core on the BeagleV-Fire FPGA fabric, which will be functionally equivalent to a PRU subsystem on the BeagleBone Black. Together with ultra-low latency I/O operations, this core will be able to execute Risc-V instructions acting as a microcontroller. BeagleV-Fire will feature a functional PRU-comparable subsystem on its FPGA fabric by the project's conclusion.
 
-The programmable nature of the PRU, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the system-on-chip (SoC).
-This is a basic block diagram for PRU design: 
+The main aim of this project is to deploy a soft core subsystem on BeagleV-Fire’s FPGA fabric, functionally equivalent to PRU subsystem on BeagleBone Black. The core will feature RISC-V ISA customised to perform ultra low-latency I/O operations, i.e., single-cycle execution. This deployment will provide high-bandwidth data transfer in main CPU and I/O and also ensure high speed data processing similar to a microcontroller.
+
+The programmable nature of the PRU, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time responses, specialised data handling operations, custom peripheral interfaces, and in offloading tasks from the main processor cores of the system-on-chip (SoC).
 
 .. image:: ../_static/images/PRU_diagram.png 
 
-Based on the block diagram above we can divide the project into two stages.
-Stage 1 will include deciding the most suitable pre-existing core based on its performance concerning its size, complexity, accessibility, etc.
-Customizing the core to meet project requirements and integrating it with BeagleV-Fire gateware, followed by extensive Verification of the modifications using preset verification techniques.  
-This stage will conclude with having a stable communication protocol between the PRU and main CPU. This will ensure that the PRU's instruction memory can be written by main CPU and have an interrupt signal to control the PRU.
+Based on the requirements of the project, it is most efficient to use PicoRV (an open source RISC-V based processor) as a base and modify it to perform high speed I/O operations. The PicoRV possesses excellent compiler support and diverse instruction set but lacks I/O support and single-cycle execution for some instructions.
+
+This problem will be resolved within the first stage of the project, which will focus on making the core I/O compatible and modifying its execution flow to ensure single-cycle execution for all instructions. Some present soft processor IPs like AMD’s Microblaze used in Vivado Design Suite and Microchip’s Mi-V used in Libero Design suite can provide good insights on how a functioning soft core IP will look like.
+As the Stage-1 of this project concludes with deployment of the RV core, Stage-2 will focus on establishing a communication medium between the PRU and the main CPU. This will ensure the ‘on-the-fly’ programming for the PRU and high bandwidth data transfer from I/O to the main CPU.
+
+riscv64-unknown-elf-gcc compiler will compile the C program into bare-metal RISC-V based binary instructions within the linux booted on the main CPU. The communication between main CPU and PRU will be used to send these instructions into the program memory of PRU without needing to flash the FPGA each time.
+
+ This connection can be established in multiple ways: 
 
-At Stage 1 Evaluation, a functional Risc-V PRU with CPU access support will be prepared for deployment.  
+1. The Program Memory of the PRU can be written into SPI flash that contains FPGA logic, and the data transfer will take place through 32-bit interconnecting AXI bus.
+2. Shared memory between PRU and Main CPU can be used of PRU memory and Data Transfer.
+3. 32-bit interconnecting AXI bus can be used to write instructions into Program memory of PRU which will be printed on FPGA logic, the same AXI bus will be used for other Data Transfers.
 
-The primary aim for Stage 2 will be establishing the necessary I/O functions, and stable communication between the PRU and these I/O.
-I/O and other peripherals can be mapped to particular special addresses to which the PRU can write, which will enable the user to configure the I/O devices to any parameters using a PRU C Library, which will try to abstract I/O usage for the user.
-Changes to be made to build scripts to add an option of including a PRU design to the gateware when flashing the Board. Updating Device Tree Overlay to enable PRU whenever necessary. Having a test program for users to get familiar with the use of PRU.
+The 32-bit interconnecting AXI bus is more suitable for burst write data to RAMs, thus using shared memory or SPI flash makes suitable method to serve as a communication medium between PRU and CPU to ensure efficient and smooth processing.
 
-After Stage 2, BeagleV-Fire will host a fully functional PRU system that can be controlled by invoking a specific function within the main CPU.
+At the conclusion of the project, BeagleV-Fire will host a fully functional PRU system that can be controlled and programmed through the main CPU.
 
 Software
 =========
@@ -150,37 +155,36 @@ Coding begins (May 27th)
 Milestone #1, Introductory YouTube video (June 3rd)
 -----------------------------------------------------
  - Make an introductory video
- - Selecting the best-suited core by comparing their functionality, size, availability of extensions, etc.
+ - Researching through other soft core IPs to understand the I/O interfacing used in the core.
  - Setting up remote access on BeagleV-Fire and completing the LED-blink tutorial given in the documentation.
 
 .. _RVFMilestone2:
 
-Milestone #2, Modifiying RV core (June 10th)
+Milestone #2, Modifiying RV core of I/O(June 10th)
 -------------------------------------------------------
- - Modification of the selected core to meet project requirements, like memory configurations, interrupt control, etc.
+ - Modification of the PicoRV core to interface GPIOs and memory.
  - Removing unnecessary extensions to reduce size and complexity, without changing its efficiency.
 
 .. _RVFMilestone3:
 
-Milestone #3, Verification of core (June 17th)
+Milestone #3, Modifying RV core for single-cycle execution(June 17th)
 -------------------------------------------------------
- - Performing Verification of PRU core using pre-determined verification methods by using Verilator or any other Verification software.
+ - Modification of the PicoRV core for single-cycle execution of all instructions.
  - This is to make sure the PRU functions as required after modifications.  
 
 .. _RVFMilestone4:
 
-Milestone #4, Remote-proc setup (June 24th)
+Milestone #4, BeagleV-Fire setup (June 24th)
 -------------------------------------------------------
- - Integration of PRU core with BeagleV-Fire gateware. This is to ensure PRU deployment through BeagleV-Fire gateware.
- - Set up Remote-proc Interfacing between PRU and main CPU. This will ensure CPU access to PRU's instruction memory.
+ - Integration of PRU core with BeagleV-Fire gateware to ensure PRU deployment through gateware.
+ - Temporary setup the program memory on FPGA logic for testing and verification of the core.
 
 .. _RVFMilestone5:
 
-Milestone #5, Setup Device Tree (July 1st)
+Milestone #5, Verification of the core (July 1st)
 -------------------------------------------------------
- - Coninuing to work on Remote-proc framework.
- - Ensuring stable PRU workflow. 
- - Setting up Device Tree Overlay to include PRU when necessary.
+ - Verification of all modifications to ensure correct instruction execution. This will be done using predefined verification methods.
+ - Ensuring stable PRU workflow.
 
 Submit midterm evaluations (July 8th)
 -------------------------------------------------------
@@ -192,31 +196,31 @@ Submit midterm evaluations (July 8th)
 
 .. _RVFMilestone6:
 
-Milestone #6, Mapping I/O (July 15th)
+Milestone #6, Establishing communication (July 15th)
 -------------------------------------------------------
- - Implementing required I/O functionalities.
- - Mapping I/O to registers to enable interaction with CPU. 
+ - Setup the program memory of the PRU within SPI flash as FPGA.
+ - Setting AXI bus access for data transfer.
 
 .. _RVFMilestone7:
 
-Milestone #7, Verification of mapped I/O (July 22nd)
+Milestone #7, Establishing communication (July 22nd)
 -------------------------------------------------------
- - Verification of these I/O operations using simulation and generating common use cases.
- - Deploying these modules on BeagleV-Fire FPGA and testing their latency and real-time application. 
+ - Using Shared memory for data transfer and comparing the results with using AXI bus and selecting faster and reliable option.
 
 .. _RVFMilestone8:
 
-Milestone #8, Add customizability (July 29th)
+Milestone #8, Setup Access (July 29th)
 -------------------------------------------------------
- - Adding customizability to CPU. This is to allow user to make small changes to CPU to observe the changes in output.
- - This will allow user to learn internal working of a RISC processor. 
+ - Setting up a easy build script to compile the C program and send it to PRU's Program Memory.
+ - Necessary changes to TCL scripts and Device Tree. 
 
 .. _RVFMilestone9:
 
-Milestone #9, Setup Scripts (Aug 5th)
+Milestone #9, Testing and Verification(Aug 5th)
 -------------------------------------------------------
- - Setting up gateware scripts wherever changes are needed. This will grant users easier access to CPU.
- - Editing TCL scripts wherever necessary.
+ - Setting up gitlab CI/CD to include necessary files in the archives.
+ - Testing smooth and easy workflow from C program to execution in PRU.
+ - Testing the GPIO bandwidth and CPU resources with and without the use of PRU. 
 
 .. _RVFMilestone10:
 
@@ -274,8 +278,7 @@ Contingency
 If I get stuck on my project and my mentor isn’t around, I will use the following resources:-
  - `BeagleV-Fire <https://docs.beagleboard.io/latest/boards/beaglev/fire/index.html>`_
  - `PRU-Documentation <https://inst.eecs.berkeley.edu/~ee192/sp20/files/am335x-pru.pdf>`_
- - `Picorv32 Docs <https://github.com/YosysHQ/picorv32/blob/master/README.md>`_
- - `VexRiscv Docs <https://github.com/SpinalHDL/VexRiscv/blob/master/README.md>`_ 
+ - `Picorv32 Docs <https://github.com/YosysHQ/picorv32/blob/master/README.md>`_ 
  - `PRU cookbook <https://docs.beagleboard.org/books/pru-cookbook/index.html>`_
  - `TI PRU documentation <https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/09_00_00_03/exports/docs/linux/Foundational_Components_PRU_Subsystem.html>`_