Atharva Kashalkar · Deepak Khatri
--- a/proposals/RISC-V_CPU_core_in_FPGA_fabric.rst
+++ b/proposals/RISC-V_CPU_core_in_FPGA_fabric.rst
+The main aim of this project is to deploy a soft core subsystem on BeagleV-Fire’s FPGA fabric, functionally equivalent to PRU subsystem on BeagleBone Black. The core will feature RISC-V ISA customised to perform ultra low-latency I/O operations, i.e., single-cycle execution. This deployment will provide high-bandwidth data transfer in main CPU and I/O and also ensure high speed data processing similar to a microcontroller.
+
+The programmable nature of the PRU, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time responses, specialised data handling operations, custom peripheral interfaces, and in offloading tasks from the main processor cores of the system-on-chip (SoC).

 .. image:: ../_static/images/PRU_diagram.png 

-Based on the block diagram above we can divide the project into two stages.
-Stage 1 will include deciding the most suitable pre-existing core based on its performance concerning its size, complexity, accessibility, etc.
-Customizing the core to meet project requirements and integrating it with BeagleV-Fire gateware, followed by extensive Verification of the modifications using preset verification techniques.  
-This stage will conclude with having a stable communication protocol between the PRU and main CPU. This will ensure that the PRU's instruction memory can be written by main CPU and have an interrupt signal to control the PRU.
+Based on the requirements of the project, it is most efficient to use PicoRV (an open source RISC-V based processor) as a base and modify it to perform high speed I/O operations. The PicoRV possesses excellent compiler support and diverse instruction set but lacks I/O support and single-cycle execution for some instructions.
+
+This problem will be resolved within the first stage of the project, which will focus on making the core I/O compatible and modifying its execution flow to ensure single-cycle execution for all instructions. Some present soft processor IPs like AMD’s Microblaze used in Vivado Design Suite and Microchip’s Mi-V used in Libero Design suite can provide good insights on how a functioning soft core IP will look like.
+As the Stage-1 of this project concludes with deployment of the RV core, Stage-2 will focus on establishing a communication medium between the PRU and the main CPU. This will ensure the ‘on-the-fly’ programming for the PRU and high bandwidth data transfer from I/O to the main CPU.
+
+*riscv64-unknown-elf-gcc* compiler will compile the C program into bare-metal RISC-V based binary instructions within the linux booted on the main CPU. The communication between main CPU and PRU will be used to send these instructions into the program memory of PRU without needing to flash the FPGA each time.