updated the cape

559f3961 · Saish Karole · 5f4a9b3b · 559f3961
Commit 559f3961 authored 11 months ago by Saish Karole
--- a/sources/FPGA-design/script_support/components/CAPE/FIRST_CAPE/device-tree-overlay/verilog-cape.dtso
+++ b/sources/FPGA-design/script_support/components/CAPE/FIRST_CAPE/device-tree-overlay/verilog-cape.dtso
@@ -6,7 +6,7 @@

 &{/chosen} {
 	overlays {
-		FIRST-CAPE-GATEWARE = "GATEWARE_GIT_VERSION";
+		FIRST-CAPE = "GATEWARE_GIT_VERSION";
 	};
 };