custom-fpga-design/my_custom_fpga_design.yaml

...gn/script_support/components/CAPE/FIRST_CAPE/ADD_CAPE.tcl

...sign/script_support/components/CAPE/FIRST_CAPE/HDL/CAPE.v

...script_support/components/CAPE/FIRST_CAPE/HDL/P8_IOPADS.v

..._support/components/CAPE/FIRST_CAPE/HDL/P9_11_18_IOPADS.v

..._support/components/CAPE/FIRST_CAPE/HDL/P9_21_31_IOPADS.v

..._support/components/CAPE/FIRST_CAPE/HDL/P9_41_42_IOPADS.v

..._support/components/CAPE/FIRST_CAPE/HDL/apb_ctrl_status.v

...ign/script_support/components/CAPE/FIRST_CAPE/HDL/blink.v

...t_support/components/CAPE/FIRST_CAPE/constraints/cape.pdc

...nts/CAPE/FIRST_CAPE/device-tree-overlay/verilog-cape.dtso