Forum | Documentation | Website | Blog

Skip to content
Snippets Groups Projects
Verified Commit 64fe066a authored by Zain Siddavatam's avatar Zain Siddavatam :fire:
Browse files

Fixes to get Fabric DMA working

parent 8d45d74e
Branches main
No related merge requests found
Pipeline #18727 passed with stages
in 8 minutes and 12 seconds
......@@ -3,13 +3,15 @@ MPFS_ICICLE_I2C_LOOPBACK/
MPFS_ICICLE_SPI_LOOPBACK/
MPFS_ICICLE_Vectorblox/
MPFS_ICICLE_DRI_CCC_DEMO/
script_support/components/MSS/
script_support/components/MSS_I2C_LOOPBACK/
script_support/components/MSS_SPI_LOOPBACK/
script_support/additional_configurations/I2C_LOOPBACK/ICICLE_MSS_I2C_LOOPBACK.cfg
script_support/additional_configurations/SPI_LOOPBACK/ICICLE_MSS_SPI_LOOPBACK.cfg
sources/FPGA-design/script_support/components/MSS/
sources/FPGA-design/script_support/components/MSS_I2C_LOOPBACK/
sources/FPGA-design/script_support/components/MSS_SPI_LOOPBACK/
sources/FPGA-design/script_support/additional_configurations/I2C_LOOPBACK/ICICLE_MSS_I2C_LOOPBACK.cfg
sources/FPGA-design/script_support/additional_configurations/SPI_LOOPBACK/ICICLE_MSS_SPI_LOOPBACK.cfg
*.hex
*.job
*.digest
work/
__pycache__/
build_log.txt
bitstream/
\ No newline at end of file
puts "==================== Add MEM_INTERFACE option: DEFAULT ===================="
download_core -vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.111} -location {www.microchip-ip.com/repositories/SgCore}
#Sourcing the Tcl files in which HDL+ core definitions are created for HDL modules
source script_support/components/MEM_INTERFACE/DEFAULT/AXI4_STREAM_DATA_GENERATOR.tcl
build_design_hierarchy
......@@ -32,17 +33,14 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {MEM_INTERFACE} -in
puts "==================== Connect MEM_INTERFACE_0 to the rest of the design ===================="
#sd_disconnect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_0_ACLK" "CLOCKS_AND_RESETS:FIC_0_ACLK" "BVF_RISCV_SUBSYSTEM:FIC_3_PCLK" "CLOCKS_AND_RESETS:FIC_3_PCLK" "BVF_RISCV_SUBSYSTEM:PRESETN" "CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "CLOCKS_AND_RESETS:FIC_0_FABRIC_RESET_N" "PHY_RSTn" "USB0_RESETB"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_0_ACLK" "FPGA_MEM_INTERFACE_0:ACLOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "FPGA_MEM_INTERFACE_0:PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_0_ACLK" "FPGA_MEM_INTERFACE_0:ACLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_3" "FPGA_MEM_INTERFACE_0:DMA_CONTROLLER_IRQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "FPGA_MEM_INTERFACE_0:PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_0_FABRIC_RESET_N" "FPGA_MEM_INTERFACE_0:ARESETN"}
#---------------------------------------------------------------------------------
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_0_AXI4_INITIATOR" "FPGA_MEM_INTERFACE_0:AXI4mmaster0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_0_AXI4_TARGET" "FPGA_MEM_INTERFACE_0:AXI4mslave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FPGA_DMA_APB_MTARGET" "FPGA_MEM_INTERFACE_0:APB_TARGET" }
#---------------------------------------------------------------------------------
# Settings to make the design compile
......
......@@ -4,7 +4,7 @@
# Create and Configure the core component DMA_CONTROLLER
create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.1.102} -component_name {DMA_CONTROLLER} -params {\
"AXI4_STREAM_IF:true" \
"AXI_DMA_DWIDTH:64" \
"AXI_DMA_DWIDTH:32" \
"DSCRPTR_0_INT_ASSOC:0" \
"DSCRPTR_0_PRI_LVL:0" \
"DSCRPTR_1_INT_ASSOC:0" \
......@@ -76,7 +76,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.1
"INT_2_QUEUE_DEPTH:1" \
"INT_3_QUEUE_DEPTH:1" \
"NUM_INT_BDS:4" \
"NUM_OF_INTS:4" \
"NUM_OF_INTS:1" \
"NUM_PRI_LVLS:1" \
"PRI_0_NUM_OF_BEATS:256" \
"PRI_1_NUM_OF_BEATS:128" \
......
......@@ -10,7 +10,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.
"ID_WIDTH:8" \
"MASTER0_CHAN_RS:true" \
"MASTER0_CLOCK_DOMAIN_CROSSING:false" \
"MASTER0_DATA_WIDTH:64" \
"MASTER0_DATA_WIDTH:32" \
"MASTER0_DWC_DATA_FIFO_DEPTH:16" \
"MASTER0_READ_INTERLEAVE:false" \
"MASTER0_READ_SLAVE0:true" \
......
......@@ -1144,7 +1144,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.
"SLAVE0_READ_INTERLEAVE:false" \
"SLAVE0_START_ADDR:0x60010000" \
"SLAVE0_START_ADDR_UPPER:0x0" \
"SLAVE0_TYPE:0" \
"SLAVE0_TYPE:1" \
"SLAVE1_CHAN_RS:true" \
"SLAVE1_CLOCK_DOMAIN_CROSSING:false" \
"SLAVE1_DATA_WIDTH:64" \
......
......@@ -6,10 +6,7 @@ create_smartdesign -sd_name ${sd_name}
auto_promote_pad_pins -promote_all 0
# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {ACLOCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PENABLE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSEL} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PWRITE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ACLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_ARVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_AWVALID} -port_direction {IN}
......@@ -23,11 +20,7 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BVALID}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSLVERR} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_ARREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_AWREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_BVALID} -port_direction {OUT}
......@@ -44,8 +37,6 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {DMA_CONTROLLER_IRQ} -port_
# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PWDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_ARADDR} -port_direction {IN} -port_range {[37:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_ARBURST} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_ARCACHE} -port_direction {IN} -port_range {[3:0]}
......@@ -71,15 +62,14 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_AWUSER}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_WDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_WSTRB} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_WUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BID} -port_direction {IN} -port_range {[8:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RID} -port_direction {IN} -port_range {[8:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PRDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_BID} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_BRESP} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_BUSER} -port_direction {OUT} -port_range {[0:0]}
......@@ -90,7 +80,7 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mmaster0_MASTER0_RUSER} -
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARID} -port_direction {OUT} -port_range {[8:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARPROT} -port_direction {OUT} -port_range {[2:0]}
......@@ -101,7 +91,7 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARUSER} -p
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWID} -port_direction {OUT} -port_range {[8:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWPROT} -port_direction {OUT} -port_range {[2:0]}
......@@ -115,62 +105,6 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_WUSER} -po
# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {APB_TARGET} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"PADDR:APB_TARGET_PADDR" \
"PSELx:APB_TARGET_PSEL" \
"PENABLE:APB_TARGET_PENABLE" \
"PWRITE:APB_TARGET_PWRITE" \
"PRDATA:APB_TARGET_PRDATA" \
"PWDATA:APB_TARGET_PWDATA" \
"PREADY:APB_TARGET_PREADY" \
"PSLVERR:APB_TARGET_PSLVERR" }
sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave0} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave0_SLAVE0_AWID" \
"AWADDR:AXI4mslave0_SLAVE0_AWADDR" \
"AWLEN:AXI4mslave0_SLAVE0_AWLEN" \
"AWSIZE:AXI4mslave0_SLAVE0_AWSIZE" \
"AWBURST:AXI4mslave0_SLAVE0_AWBURST" \
"AWLOCK:AXI4mslave0_SLAVE0_AWLOCK" \
"AWCACHE:AXI4mslave0_SLAVE0_AWCACHE" \
"AWPROT:AXI4mslave0_SLAVE0_AWPROT" \
"AWQOS:AXI4mslave0_SLAVE0_AWQOS" \
"AWREGION:AXI4mslave0_SLAVE0_AWREGION" \
"AWVALID:AXI4mslave0_SLAVE0_AWVALID" \
"AWREADY:AXI4mslave0_SLAVE0_AWREADY" \
"WDATA:AXI4mslave0_SLAVE0_WDATA" \
"WSTRB:AXI4mslave0_SLAVE0_WSTRB" \
"WLAST:AXI4mslave0_SLAVE0_WLAST" \
"WVALID:AXI4mslave0_SLAVE0_WVALID" \
"WREADY:AXI4mslave0_SLAVE0_WREADY" \
"BID:AXI4mslave0_SLAVE0_BID" \
"BRESP:AXI4mslave0_SLAVE0_BRESP" \
"BVALID:AXI4mslave0_SLAVE0_BVALID" \
"BREADY:AXI4mslave0_SLAVE0_BREADY" \
"ARID:AXI4mslave0_SLAVE0_ARID" \
"ARADDR:AXI4mslave0_SLAVE0_ARADDR" \
"ARLEN:AXI4mslave0_SLAVE0_ARLEN" \
"ARSIZE:AXI4mslave0_SLAVE0_ARSIZE" \
"ARBURST:AXI4mslave0_SLAVE0_ARBURST" \
"ARLOCK:AXI4mslave0_SLAVE0_ARLOCK" \
"ARCACHE:AXI4mslave0_SLAVE0_ARCACHE" \
"ARPROT:AXI4mslave0_SLAVE0_ARPROT" \
"ARQOS:AXI4mslave0_SLAVE0_ARQOS" \
"ARREGION:AXI4mslave0_SLAVE0_ARREGION" \
"ARVALID:AXI4mslave0_SLAVE0_ARVALID" \
"ARREADY:AXI4mslave0_SLAVE0_ARREADY" \
"RID:AXI4mslave0_SLAVE0_RID" \
"RDATA:AXI4mslave0_SLAVE0_RDATA" \
"RRESP:AXI4mslave0_SLAVE0_RRESP" \
"RLAST:AXI4mslave0_SLAVE0_RLAST" \
"RVALID:AXI4mslave0_SLAVE0_RVALID" \
"RREADY:AXI4mslave0_SLAVE0_RREADY" \
"AWUSER:AXI4mslave0_SLAVE0_AWUSER" \
"WUSER:AXI4mslave0_SLAVE0_WUSER" \
"BUSER:AXI4mslave0_SLAVE0_BUSER" \
"ARUSER:AXI4mslave0_SLAVE0_ARUSER" \
"RUSER:AXI4mslave0_SLAVE0_RUSER" }
sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mmaster0} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredMaster} -port_bif_mapping {\
"AWID:AXI4mmaster0_MASTER0_AWID" \
"AWADDR:AXI4mmaster0_MASTER0_AWADDR" \
......@@ -217,26 +151,66 @@ sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mmaster0} -port_bif_vlnv
"ARUSER:AXI4mmaster0_MASTER0_ARUSER" \
"RUSER:AXI4mmaster0_MASTER0_RUSER" }
# Add AXI4_STREAM_DATA_GENERATOR_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4_STREAM_DATA_GENERATOR} -instance_name {AXI4_STREAM_DATA_GENERATOR_0}
sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave0} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave0_SLAVE0_AWID" \
"AWADDR:AXI4mslave0_SLAVE0_AWADDR" \
"AWLEN:AXI4mslave0_SLAVE0_AWLEN" \
"AWSIZE:AXI4mslave0_SLAVE0_AWSIZE" \
"AWBURST:AXI4mslave0_SLAVE0_AWBURST" \
"AWLOCK:AXI4mslave0_SLAVE0_AWLOCK" \
"AWCACHE:AXI4mslave0_SLAVE0_AWCACHE" \
"AWPROT:AXI4mslave0_SLAVE0_AWPROT" \
"AWQOS:AXI4mslave0_SLAVE0_AWQOS" \
"AWREGION:AXI4mslave0_SLAVE0_AWREGION" \
"AWVALID:AXI4mslave0_SLAVE0_AWVALID" \
"AWREADY:AXI4mslave0_SLAVE0_AWREADY" \
"WDATA:AXI4mslave0_SLAVE0_WDATA" \
"WSTRB:AXI4mslave0_SLAVE0_WSTRB" \
"WLAST:AXI4mslave0_SLAVE0_WLAST" \
"WVALID:AXI4mslave0_SLAVE0_WVALID" \
"WREADY:AXI4mslave0_SLAVE0_WREADY" \
"BID:AXI4mslave0_SLAVE0_BID" \
"BRESP:AXI4mslave0_SLAVE0_BRESP" \
"BVALID:AXI4mslave0_SLAVE0_BVALID" \
"BREADY:AXI4mslave0_SLAVE0_BREADY" \
"ARID:AXI4mslave0_SLAVE0_ARID" \
"ARADDR:AXI4mslave0_SLAVE0_ARADDR" \
"ARLEN:AXI4mslave0_SLAVE0_ARLEN" \
"ARSIZE:AXI4mslave0_SLAVE0_ARSIZE" \
"ARBURST:AXI4mslave0_SLAVE0_ARBURST" \
"ARLOCK:AXI4mslave0_SLAVE0_ARLOCK" \
"ARCACHE:AXI4mslave0_SLAVE0_ARCACHE" \
"ARPROT:AXI4mslave0_SLAVE0_ARPROT" \
"ARQOS:AXI4mslave0_SLAVE0_ARQOS" \
"ARREGION:AXI4mslave0_SLAVE0_ARREGION" \
"ARVALID:AXI4mslave0_SLAVE0_ARVALID" \
"ARREADY:AXI4mslave0_SLAVE0_ARREADY" \
"RID:AXI4mslave0_SLAVE0_RID" \
"RDATA:AXI4mslave0_SLAVE0_RDATA" \
"RRESP:AXI4mslave0_SLAVE0_RRESP" \
"RLAST:AXI4mslave0_SLAVE0_RLAST" \
"RVALID:AXI4mslave0_SLAVE0_RVALID" \
"RREADY:AXI4mslave0_SLAVE0_RREADY" \
"AWUSER:AXI4mslave0_SLAVE0_AWUSER" \
"WUSER:AXI4mslave0_SLAVE0_WUSER" \
"BUSER:AXI4mslave0_SLAVE0_BUSER" \
"ARUSER:AXI4mslave0_SLAVE0_ARUSER" \
"RUSER:AXI4mslave0_SLAVE0_RUSER" }
# Add DMA_CONTROLLER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DMA_CONTROLLER} -instance_name {DMA_CONTROLLER_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:INTERRUPT} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:INTERRUPT} -pin_slices {[3:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:INTERRUPT[3:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:TDATA} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:TDATA} -pin_slices {[63:32]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TDATA[63:32]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:TSTRB} -pin_slices {[3:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:TSTRB} -pin_slices {[7:4]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TSTRB[7:4]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:TKEEP} -pin_slices {[3:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:TKEEP} -pin_slices {[7:4]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TKEEP[7:4]} -value {GND}
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:INTERRUPT} -pin_slices {[0:0]}
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {DMA_CONTROLLER_0:INTERRUPT} -pin_slices {[3:1]}
#sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:INTERRUPT[3:1]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TVALID} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TREADY}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TLAST} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:STRTDMAOP} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TDATA} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TSTRB} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TKEEP} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TID} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DMA_CONTROLLER_0:TDEST} -value {GND}
......@@ -256,24 +230,12 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {MSS_LSRAM} -instan
# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ACLOCK" "AXI4_STREAM_DATA_GENERATOR_0:ACLK" "DMA_CONTROLLER_0:CLOCK" "DMA_INITIATOR_0:ACLK" "FIC_0_INITIATOR_0:ACLK" "MSS_LSRAM_0:ACLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARESETN" "AXI4_STREAM_DATA_GENERATOR_0:RSTN" "DMA_CONTROLLER_0:RESETN" "DMA_INITIATOR_0:ARESETN" "FIC_0_INITIATOR_0:ARESETN" "MSS_LSRAM_0:ARESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:PCLK" "PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:PRESETN" "PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:TLAST" "DMA_CONTROLLER_0:TLAST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:TREADY" "DMA_CONTROLLER_0:TREADY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:TVALID" "DMA_CONTROLLER_0:TVALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_CONTROLLER_0:INTERRUPT[0:0]" "DMA_CONTROLLER_IRQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ACLK" "DMA_CONTROLLER_0:CLOCK" "DMA_INITIATOR_0:ACLK" "FIC_0_INITIATOR_0:ACLK" "MSS_LSRAM_0:ACLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARESETN" "DMA_CONTROLLER_0:RESETN" "DMA_INITIATOR_0:ARESETN" "FIC_0_INITIATOR_0:ARESETN" "MSS_LSRAM_0:ARESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_CONTROLLER_0:INTERRUPT" "DMA_CONTROLLER_IRQ" }
# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:TDATA" "DMA_CONTROLLER_0:TDATA[31:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:TDEST" "DMA_CONTROLLER_0:TDEST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:TID" "DMA_CONTROLLER_0:TID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:TKEEP" "DMA_CONTROLLER_0:TKEEP[3:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_STREAM_DATA_GENERATOR_0:TSTRB" "DMA_CONTROLLER_0:TSTRB[3:0]" }
# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_TARGET" "AXI4_STREAM_DATA_GENERATOR_0:APB_TARGET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mmaster0" "FIC_0_INITIATOR_0:AXI4mmaster0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave0" "DMA_INITIATOR_0:AXI4mslave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DMA_CONTROLLER_0:AXI4MasterDMA_IF" "DMA_INITIATOR_0:AXI4mmaster0" }
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment