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Commit 1b5a0051 authored by Vauban's avatar Vauban
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Libero version: Reduce base IP blocks dependence on Libero version.

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with 30 additions and 30 deletions
......@@ -128,17 +128,17 @@ new_project \
# // Download required cores
#
download_core -vlnv {Actel:SgCore:PF_OSC:1.0.102} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_OSC:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_CCC:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.304} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CORERESET_PF:*} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_DRI:1.1.104} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_NGMUX:1.0.101} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_CLK_DIV:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_DRI:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_NGMUX:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_PCIE:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_TX_PLL:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
#download_core -vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
......@@ -148,9 +148,9 @@ download_core -vlnv {Actel:Simulation:RESET_GEN:1.0.1} -location {www.microchip-
download_core -vlnv {Actel:DirectCore:corepwm:4.5.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREI2C:7.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.109} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_IO:2.0.104} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_IO:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -location {www.microchip-ip.com/repositories/SgCore}
#
# // Generate base design
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component CLK_DIV
create_and_configure_core -core_vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -component_name {CLK_DIV} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_CLK_DIV:*} -component_name {CLK_DIV} -params {\
"DIVIDER:2" \
"ENABLE_BIT_SLIP:false" \
"ENABLE_SRESET:false" }
......
......@@ -2,6 +2,6 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component GLITCHLESS_MUX
create_and_configure_core -core_vlnv {Actel:SgCore:PF_NGMUX:1.0.101} -component_name {GLITCHLESS_MUX} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_NGMUX:*} -component_name {GLITCHLESS_MUX} -params {\
"ENABLE_NON_TOGGLING_CLK_SWITCH_SUPPORT:false" }
# Exporting Component Description of GLITCHLESS_MUX to TCL done
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component INIT_MONITOR
create_and_configure_core -core_vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.304} -component_name {INIT_MONITOR} -params {\
create_and_configure_core -core_vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:*} -component_name {INIT_MONITOR} -params {\
"BANK_0_CALIB_STATUS_ENABLED:false" \
"BANK_0_CALIB_STATUS_SIMULATION_DELAY:1" \
"BANK_0_RECALIBRATION_ENABLED:false" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component OSCILLATOR_160MHz
create_and_configure_core -core_vlnv {Actel:SgCore:PF_OSC:1.0.102} -component_name {OSCILLATOR_160MHz} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_OSC:*} -component_name {OSCILLATOR_160MHz} -params {\
"RCOSC_2MHZ_CLK_DIV_EN:false" \
"RCOSC_2MHZ_GL_EN:false" \
"RCOSC_2MHZ_NGMUX_EN:false" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component PCIE_REF_CLK
create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PCIE_REF_CLK} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PCIE_REF_CLK} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component TRANSMIT_PLL
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {TRANSMIT_PLL} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {TRANSMIT_PLL} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_TX_PLL_C0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_C0} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_C0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_XCVR_REF_CLK_C0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_CLK_DIV_C0
create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:1.0.103 -component_name {PF_CLK_DIV_C0} -params {\
create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:* -component_name {PF_CLK_DIV_C0} -params {\
"DIVIDER:4" \
"ENABLE_BIT_SLIP:false" \
"ENABLE_SRESET:false" }
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_TX_PLL_0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_0} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_XCVR_0
create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_0} -params {\
create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_0} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_XCVR_REF_CLK_0
create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:1.0.103 -component_name {PF_XCVR_REF_CLK_0} -params {\
create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:* -component_name {PF_XCVR_REF_CLK_0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484E
# Create and Configure the core component PF_XCVR_REF_CLK_C0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
"ENABLE_FAB_CLK_0:true" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_CLK_DIV_C0
create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:1.0.103 -component_name {PF_CLK_DIV_C0} -params {\
create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:* -component_name {PF_CLK_DIV_C0} -params {\
"DIVIDER:4" \
"ENABLE_BIT_SLIP:false" \
"ENABLE_SRESET:false" }
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_TX_PLL_0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_0} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_XCVR_0
create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_0} -params {\
create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_0} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_XCVR_REF_CLK_0
create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:1.0.103 -component_name {PF_XCVR_REF_CLK_0} -params {\
create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:* -component_name {PF_XCVR_REF_CLK_0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484E
# Create and Configure the core component PF_XCVR_REF_CLK_C0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
"ENABLE_FAB_CLK_0:true" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
......
......@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_CLK_DIV_C0
create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:1.0.103 -component_name {PF_CLK_DIV_C0} -params {\
create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:* -component_name {PF_CLK_DIV_C0} -params {\
"DIVIDER:4" \
"ENABLE_BIT_SLIP:false" \
"ENABLE_SRESET:false" }
......
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