- May 30, 2024
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berlinerblaw1 authored
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- May 29, 2024
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berlinerblaw1 authored
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berlinerblaw1 authored
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- May 15, 2024
- Apr 21, 2024
- Apr 07, 2024
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Vauban authored
Regenerate the debian-custom/bbb.io-gateware-my-custom-fpga-design.install file to include multiple custom gatewares programming files in the generated package.
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- Apr 05, 2024
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- Mar 18, 2024
- Mar 15, 2024
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Vauban authored
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- Mar 14, 2024
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Vauban authored
Restore stdout to its original value at the end of a gateware build to ensure that successive builds do not result in the log for one build bleeding into a subsequent build when creating a release.
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Vauban authored
Gateware build is taking place in a different location. Pick upo build from modified location.
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Vauban authored
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- Mar 13, 2024
- Mar 11, 2024
- Feb 25, 2024
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Vauban authored
Ensure version generated from date time is below 0xFFFF to prevent modulo 65536 of the generated value causing failure to work out the time at which the design was generated.
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- Feb 24, 2024
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Vauban authored
Remove the need to update the unique-design-version entry in the build option YAML file between builds to ensure successful FPGA programming. An FPGA design version based on the date and time is generated when no unique-design-version is specified simplifying interactive build/debug cycles.
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- Feb 13, 2024
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Aven Arlington authored
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Aven Arlington authored
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- Feb 11, 2024
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Vauban authored
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- Jan 19, 2024
- Dec 28, 2023
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Vauban authored
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- Dec 26, 2023
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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- Dec 19, 2023
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Vauban authored
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- Dec 10, 2023
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Vauban authored
BeagleV-Fire uses the PolarFire-Soc IAP feature to reprogram the SoC-FPGA from Linux. The IAP mode used only actually programs the device if the Libero design version is different from the one in the currently programmed FPGA design. This change to the gateware builder uses the gateware repo's git hash to generate a Libero design version number which will be different with each push to a forked gateware repository. This results in the bitstream generated by the CI to successfully reprogram the SoC-FPGA after each change to the gateware source code.
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- Dec 09, 2023
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Vauban authored
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- Dec 04, 2023
- Dec 03, 2023
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Vauban authored
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- Nov 22, 2023
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Vauban authored
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