Try 3. move hexfile contents into servant_ram.v
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- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_alu.v 1 addition, 1 deletion...omponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_alu.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_csr.v 1 addition, 1 deletion...omponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_csr.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_ctrl.v 1 addition, 1 deletion...mponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_ctrl.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_decode.v 1 addition, 1 deletion...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_decode.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_immdec.v 1 addition, 1 deletion...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_immdec.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_mem_if.v 1 addition, 1 deletion...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_mem_if.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_if.v 1 addition, 1 deletion...ponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_if.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_ram_if.v 1 addition, 1 deletion...nts/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_ram_if.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_top.v 2 additions, 2 deletions...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_top.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_top.v 2 additions, 2 deletions...omponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_top.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/servant_1.2.1/bench/servant_sim.v 1 addition, 1 deletion...s/CAPE/MY_SERV_CAPE/HDL/servant_1.2.1/bench/servant_sim.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/servant_1.2.1/servant/servant.v 1 addition, 1 deletion...nts/CAPE/MY_SERV_CAPE/HDL/servant_1.2.1/servant/servant.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/servant_1.2.1/servant/servant_ram.v 28 additions, 9 deletions...CAPE/MY_SERV_CAPE/HDL/servant_1.2.1/servant/servant_ram.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/servant_1.2.1/servant/servant_timer.v 1 addition, 1 deletion...PE/MY_SERV_CAPE/HDL/servant_1.2.1/servant/servant_timer.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/servile_1.3.0/servile/servile.v 2 additions, 2 deletions...nts/CAPE/MY_SERV_CAPE/HDL/servile_1.3.0/servile/servile.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/servile_1.3.0/servile/servile_rf_mem_if.v 1 addition, 1 deletion...Y_SERV_CAPE/HDL/servile_1.3.0/servile/servile_rf_mem_if.v
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