Add SERV RISC-V processor to CAPE gateware
Showing
- custom-fpga-design/my_custom_fpga_design.yaml 1 addition, 1 deletioncustom-fpga-design/my_custom_fpga_design.yaml
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/ADD_CAPE.tcl 157 additions, 0 deletions.../script_support/components/CAPE/MY_SERV_CAPE/ADD_CAPE.tcl
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/CAPE.v 472 additions, 0 deletions...gn/script_support/components/CAPE/MY_SERV_CAPE/HDL/CAPE.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/P8_IOPADS.v 1013 additions, 0 deletions...ript_support/components/CAPE/MY_SERV_CAPE/HDL/P8_IOPADS.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/P9_11_18_IOPADS.v 221 additions, 0 deletions...upport/components/CAPE/MY_SERV_CAPE/HDL/P9_11_18_IOPADS.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/P9_21_31_IOPADS.v 287 additions, 0 deletions...upport/components/CAPE/MY_SERV_CAPE/HDL/P9_21_31_IOPADS.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/P9_41_42_IOPADS.v 89 additions, 0 deletions...upport/components/CAPE/MY_SERV_CAPE/HDL/P9_41_42_IOPADS.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/apb_ctrl_status.v 73 additions, 0 deletions...upport/components/CAPE/MY_SERV_CAPE/HDL/apb_ctrl_status.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_aligner.v 67 additions, 0 deletions...nents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_aligner.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_alu.v 81 additions, 0 deletions...omponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_alu.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_bufreg.v 51 additions, 0 deletions...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_bufreg.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_bufreg2.v 65 additions, 0 deletions...nents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_bufreg2.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_compdec.v 232 additions, 0 deletions...nents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_compdec.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_csr.v 146 additions, 0 deletions...omponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_csr.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_ctrl.v 109 additions, 0 deletions...mponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_ctrl.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_decode.v 365 additions, 0 deletions...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_decode.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_immdec.v 95 additions, 0 deletions...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_immdec.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_mem_if.v 69 additions, 0 deletions...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_mem_if.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_if.v 153 additions, 0 deletions...ponents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_if.v
- sources/FPGA-design/script_support/components/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_ram.v 45 additions, 0 deletions...onents/CAPE/MY_SERV_CAPE/HDL/serv_1.2.1/rtl/serv_rf_ram.v
Please register or sign in to comment