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Created with Raphaël 2.2.010Mar91025Feb24131119Jan28Dec26191094322Nov212019113231Oct191817151211108432129Sep28272524211912Aug11623Jul22212016111Jun9430May24231413129Apr225Mar29Jan1531Dec2827Nov20108722Oct876Sep54331Aug302912Jun1086429May27818Apr25Mar13876527Feb2120181413121198FixmainmainTurn into snakeFix typoUpdate .gitlab-ci.yml fileFirstBuild scripts: Adjust date time design version generation.Build scripts: Simplify FPGA design version generationAdding a check for OS and updating function nameAdding a check for device tree compilerCape: Connect CoreGPIO interrupts.Build system: Non-Linux host support.Build system: Gracefully handle git describe failure.SYZYGY: Add 3 lanes loopback for Opal Kelly SZG-TST-TXR4.ci: build native riscv64 gateware package and deploy debian repo over gitlab pages part 2CI: Add repo parameter for updated gateware tester.CI: Use git hash as version number for custom gateware CI.Cape: Add Verilog tutorial.Cape: Verilog template: Re-order cape IOs.Cape: Verilog template: Simplify APB interface.Cape: Add Verilog template.Base design: Correct ADC_MCLK connection TCL syntax.CI: Specify CI tag for Libero version.CI: Correct CI varaible used for gateware repo.SYZYGY: Make PF_TX_PLL Libero version agnostic.CI: Update CI for re-organized gateware repository.Doc: Add Readme for gateware-builder usage.Doc: Add readme for gateware builder.Build scripts: Device tree overlay: fix gateware path.CI: Add build-option for custom FPGA design.Build scripts: Integrated bitstream-builder scripts.Libero: Move MSS configuration out of FPGA design.Libero: Move Libero scripts to sources directory.Libero: Generate DirectC programming file.Libero: Enable use of Libero 2023.2.CI: Add test repo URL argument.CI: Update to new gateware-builds-tester.Robotics cape: adjust encoder debounce.Robotics cape: Connect GPIO interupts.Base design: Promote spare interrupts to top level.Board tests: Increase LED GPIO drive strength.

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