Add the IO_BOARD_VALIDATION option to the MIPI_CSI_OPION build options.

This option generates PWM signals on the MIPI CSI interface to check
board connectivity. The PWM signals have a different increasing duty
cycle from data to clock to control signasls on the interface.

Please note this requires manual Verilog source code changes to CorePWM.
file: components/Actel/DirectCore/corepwm/4.5.100/rtl/vlog/core/reg_if.v
Lines 99 and 100 nedd to  be changed as follows:
  from:
         psh_enable_reg1  <= 0;
         psh_enable_reg2  <= 0;

  to:
         psh_enable_reg1  <= 8'b11111111;
         psh_enable_reg2  <= 8'b11111111;

Connect VIO_ENABLE control signal to MSS GPIO_2[30].

Changed APB bus address decoding as follows:
 - CorePWM:  base address 0x41000000
 - CoreGPIO: base address 0x41100000

Add HIGH_SPEED_CONN Liberop script argument to select between no high
speed connector being included in the design (NONE) or including a
design stub (IO_STUB) exposing the pins used by the high speed
connector. The later being used to validate I/O pin constraints.

- Add missing cape signals.
- Adjust M.2 and base design pin constraints to match new cape pin
  assignments
- Move immutable cape signasl pin constraints to base design's pin
  constraints file.

- Remove PCM signals
- Reduce PCIe from 2 to 1 lane.

Let I/O pads propagate to the top level of the design and rename as
required.

Couple the pin constraint files with the variant of design blocks.
This should allow us to customize cape I/Os to best suit a specific
cape. It also allows to easily include or excluse a block from the
design. For example, not include cape, M.2, MIPI-CSI or high speed
interface if not required and tight on FPGA resources.