IP update: Update IP version for PCIe block and PFSOC_INIT_MONITOR.

script_support/components/CLOCKS_AND_RESETS/INIT_MONITOR.tcl

@@ -2,7 +2,7 @@
 # Family: PolarFireSoC
 # Part Number: MPFS250T_ES-FCVG484E
 # Create and Configure the core component INIT_MONITOR
-create_and_configure_core -core_vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.205} -component_name {INIT_MONITOR} -params {\
+create_and_configure_core -core_vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.302} -component_name {INIT_MONITOR} -params {\
 "BANK_0_CALIB_STATUS_ENABLED:false"  \
 "BANK_0_CALIB_STATUS_SIMULATION_DELAY:1"  \
 "BANK_0_RECALIBRATION_ENABLED:false"  \

script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl

 # Exporting Component Description of PF_PCIE_C0 to TCL
 # Family: PolarFireSoC
-# Part Number: MPFS025T-FCVG484_EVALE
+# Part Number: MPFS025T-FCVG484E
 # Create and Configure the core component PF_PCIE_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:2.0.106} -component_name {PF_PCIE_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:2.0.116} -component_name {PF_PCIE_C0} -params {\
 "EXPOSE_ALL_DEBUG_PORTS:false"  \
 "UI_DLL_JITTER_TOLERANCE:Medium_Low"  \
 "UI_EXPOSE_LANE_DRI_PORTS:true"  \
-"UI_EXPOSE_PCIE_APBLINK_PORTS:false"  \
+"UI_EXPOSE_PCIE_APBLINK_PORTS:true"  \
 "UI_GPSS1_LANE0_IS_USED:false"  \
 "UI_GPSS1_LANE1_IS_USED:false"  \
 "UI_GPSS1_LANE2_IS_USED:false"  \
@@ -15,19 +15,19 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:2.0.106} -component_n
 "UI_PCIE_0_BAR_MODE:Custom"  \
 "UI_PCIE_0_CDR_REF_CLK_NUMBER:1"  \
 "UI_PCIE_0_CDR_REF_CLK_SOURCE:Dedicated"  \
-"UI_PCIE_0_CLASS_CODE:0x0604"  \
+"UI_PCIE_0_CLASS_CODE:0x0000"  \
 "UI_PCIE_0_CONTROLLER_ENABLED:Enabled"  \
 "UI_PCIE_0_DE_EMPHASIS:-3.5 dB"  \
 "UI_PCIE_0_DEVICE_ID:0x1556"  \
 "UI_PCIE_0_EXPOSE_WAKE_SIG:Disabled"  \
-"UI_PCIE_0_INTERRUPTS:MSI8"  \
+"UI_PCIE_0_INTERRUPTS:MSI1"  \
 "UI_PCIE_0_L0_ACC_LATENCY:No limit"  \
 "UI_PCIE_0_L0_EXIT_LATENCY:64 ns to less than 128 ns"  \
 "UI_PCIE_0_L1_ACC_LATENCY:No limit"  \
 "UI_PCIE_0_L1_ENABLE:Disabled"  \
 "UI_PCIE_0_L1_EXIT_LATENCY:16 us to less than 32 us"  \
 "UI_PCIE_0_LANE_RATE:Gen2 (5.0 Gbps)"  \
-"UI_PCIE_0_MASTER_SIZE_BAR_0_TABLE:2 GB"  \
+"UI_PCIE_0_MASTER_SIZE_BAR_0_TABLE:4 KB"  \
 "UI_PCIE_0_MASTER_SIZE_BAR_1_TABLE:4 KB"  \
 "UI_PCIE_0_MASTER_SIZE_BAR_2_TABLE:4 KB"  \
 "UI_PCIE_0_MASTER_SIZE_BAR_3_TABLE:4 KB"  \
@@ -145,7 +145,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:2.0.106} -component_n
 "UI_PCIE_1_MASTER_TYPE_BAR_4_TABLE:Disabled"  \
 "UI_PCIE_1_MASTER_TYPE_BAR_5_TABLE:Disabled"  \
 "UI_PCIE_1_NUM_FTS:63"  \
-"UI_PCIE_1_NUMBER_OF_LANES:x2"  \
+"UI_PCIE_1_NUMBER_OF_LANES:x4"  \
 "UI_PCIE_1_PHY_REF_CLK_SLOT:Slot"  \
 "UI_PCIE_1_PORT_TYPE:Root Port"  \
 "UI_PCIE_1_REF_CLK_FREQ:100"  \