This uses the Opal Kelly SYZYGY loopback test board.

Generate PWM signals on HSIO pins to check board connectivity.

Add the IO_BOARD_VALIDATION option to the MIPI_CSI_OPION build options.

This option generates PWM signals on the MIPI CSI interface to check
board connectivity. The PWM signals have a different increasing duty
cycle from data to clock to control signasls on the interface.

Please note this requires manual Verilog source code changes to CorePWM.
file: components/Actel/DirectCore/corepwm/4.5.100/rtl/vlog/core/reg_if.v
Lines 99 and 100 nedd to  be changed as follows:
  from:
         psh_enable_reg1  <= 0;
         psh_enable_reg2  <= 0;

  to:
         psh_enable_reg1  <= 8'b11111111;
         psh_enable_reg2  <= 8'b11111111;

Connect VIO_ENABLE control signal to MSS GPIO_2[30].

Changed APB bus address decoding as follows:
 - CorePWM:  base address 0x41000000
 - CoreGPIO: base address 0x41100000

Add HIGH_SPEED_CONN Liberop script argument to select between no high
speed connector being included in the design (NONE) or including a
design stub (IO_STUB) exposing the pins used by the high speed
connector. The later being used to validate I/O pin constraints.

- Add missing cape signals.
- Adjust M.2 and base design pin constraints to match new cape pin
  assignments
- Move immutable cape signasl pin constraints to base design's pin
  constraints file.