Camera PHY bringing camera data to cape pins for board validation
and debug.

The PROG_EXPORT_PATH script argument should eventually replace
FPE_EXPORT_PATH to specify the location of the generated programming
files whether for FlashProExpress, programming through Linux or using
DirectC.

Use the gateware's top level name to name the FlashPro Express job
files to ease identification of gateware variants.

The TOP_LEVEL_NAME build argument allows choosing the name of the
gateware's top level name. This can be used to identify different
variants of the gateware design.

The M2_W_DISABLEx are tied low to not de-activate wifi radio.

Adjust PCIe block configuration to match Microchip 2023.02 release.

- Clear confusionabout interrupt signal polarity by removing _N from
  PCIe interrupt signal name.
- Tie MSS PCIe interrupt signal to ground when PCIe block not
  instantiated.

- Match changes in PCIe and DDR memory layout for non-coherent DMA
  transfers across the FPGA fabric.

- Add floor placement for CCC/PLL.
- Add FPGA fabric interfaces clock groups.
- Enable timing verification as part gateware build flow.

The 2 lanes llopback allows using the M.2 PCIe port at the same time as the SYZYGY
two SERDES interfaces.

- All FPGA AXI bus clocks aet to 125MHz.
- FPGA APB bus clock set to 50MHz.

Add SYZYGY port design option allowing loopback of all 3 SERDES lanes
and SGMII interface.
Please note this design option is mutually exclusive with the M.2
default design option. use M2_OPTION:NONE when using this design option.

This was tested using the following libero script options:
libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE CAPE_OPTION:NONE HIGH_SPEED_CONN_OPTION:BOARD_VALIDATION_SEEED_STUDIO"

This uses the Opal Kelly SYZYGY loopback test board.

Generate PWM signals on HSIO pins to check board connectivity.

Add the IO_BOARD_VALIDATION option to the MIPI_CSI_OPION build options.

This option generates PWM signals on the MIPI CSI interface to check
board connectivity. The PWM signals have a different increasing duty
cycle from data to clock to control signasls on the interface.

Please note this requires manual Verilog source code changes to CorePWM.
file: components/Actel/DirectCore/corepwm/4.5.100/rtl/vlog/core/reg_if.v
Lines 99 and 100 nedd to  be changed as follows:
  from:
         psh_enable_reg1  <= 0;
         psh_enable_reg2  <= 0;

  to:
         psh_enable_reg1  <= 8'b11111111;
         psh_enable_reg2  <= 8'b11111111;

Connect VIO_ENABLE control signal to MSS GPIO_2[30].

Changed APB bus address decoding as follows:
 - CorePWM:  base address 0x41000000
 - CoreGPIO: base address 0x41100000