Commits · 8f81db35e4c72e358945bcb125a12185437a91c9 · Jason Kridner / Snakeyware

Dec 09, 2023
- Cape: Add Verilog tutorial. · 8f81db35
  Vauban authored 1 year ago
  
  8f81db35
Dec 04, 2023
- Cape: Verilog template: Re-order cape IOs. · ad2a1c42
  Vauban authored 1 year ago
  
  ad2a1c42
- Cape: Verilog template: Simplify APB interface. · c480802b
  Vauban authored 1 year ago
  
  c480802b
Dec 03, 2023
- Cape: Add Verilog template. · 8474b79e
  Vauban authored 1 year ago
  
  8474b79e
Nov 22, 2023
- Base design: Correct ADC_MCLK connection TCL syntax. · f951fce8
  Vauban authored 1 year ago
  
  f951fce8
Nov 20, 2023
- SYZYGY: Make PF_TX_PLL Libero version agnostic. · 4f1c1f8c
  Vauban authored 1 year ago
  
  4f1c1f8c
Nov 11, 2023
- Libero: Move MSS configuration out of FPGA design. · c80f4477
  Vauban authored 1 year ago
  
  c80f4477
- Libero: Move Libero scripts to sources directory. · fb1c1c2a
  Vauban authored 1 year ago
  
  fb1c1c2a

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