Commits · 7b19080e32f1014de3d79783798ebdb84232fd1a · Jason Kridner / Snakeyware

Mar 09, 2024
- Turn into snake · 7b19080e
  Platima Tinkers authored 1 year ago
  
  7b19080e
- Fix typo · 81f290ee
  Platima Tinkers authored 1 year ago
  
  81f290ee
- First · 3dcff649
  Platima Tinkers authored 1 year ago
  
  3dcff649
Feb 11, 2024
- Cape: Connect CoreGPIO interrupts. · 42e49cfd
  Vauban authored 1 year ago
  
  42e49cfd
Dec 28, 2023
- SYZYGY: Add 3 lanes loopback for Opal Kelly SZG-TST-TXR4. · 7078de96
  Vauban authored 1 year ago
  
  7078de96
Dec 09, 2023
- Cape: Add Verilog tutorial. · 8f81db35
  Vauban authored 1 year ago
  
  8f81db35
Dec 04, 2023
- Cape: Verilog template: Re-order cape IOs. · ad2a1c42
  Vauban authored 1 year ago
  
  ad2a1c42
- Cape: Verilog template: Simplify APB interface. · c480802b
  Vauban authored 1 year ago
  
  c480802b
Dec 03, 2023
- Cape: Add Verilog template. · 8474b79e
  Vauban authored 1 year ago
  
  8474b79e
Nov 22, 2023
- Base design: Correct ADC_MCLK connection TCL syntax. · f951fce8
  Vauban authored 1 year ago
  
  f951fce8
Nov 20, 2023
- SYZYGY: Make PF_TX_PLL Libero version agnostic. · 4f1c1f8c
  Vauban authored 1 year ago
  
  4f1c1f8c
Nov 11, 2023
- Libero: Move MSS configuration out of FPGA design. · c80f4477
  Vauban authored 1 year ago
  
  c80f4477
- Libero: Move Libero scripts to sources directory. · fb1c1c2a
  Vauban authored 1 year ago
  
  fb1c1c2a

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