SYZYGY port validation: Add validation design option (SEEED Studio).

Add SYZYGY port design option allowing loopback of all 3 SERDES lanes
and SGMII interface.
Please note this design option is mutually exclusive with the M.2
default design option. use M2_OPTION:NONE when using this design option.

This was tested using the following libero script options:
libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE CAPE_OPTION:NONE HIGH_SPEED_CONN_OPTION:BOARD_VALIDATION_SEEED_STUDIO"