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Commit 7b19080e authored by Platima Tinkers's avatar Platima Tinkers
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Turn into snake

parent 81f290ee
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......@@ -258,7 +258,7 @@ wire P9_41;
wire P9_42;
wire PCLK;
wire PRESETN;
wire BLINK;
wire [10:0] LEDS;
wire [31:0] APB_SLAVE_PRDATA_net_0;
wire [27:0] GPIO_IN_net_1;
wire [46:31] GPIO_IN_slice_0;
......@@ -314,8 +314,8 @@ assign GPIO_IN_slice_0 = GPIO_IN_net_2[46:31];
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign GPIO_OE_net_0 = { 16'h0000 , GPIO_OE[27:6], 1'b1, GPIO_OE[4:0] };
assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT[27:6], BLINK, GPIO_OUT[4:0] };
assign GPIO_OE_net_0 = { 16'h0000 , GPIO_OE[27:11], 11'b11111111111 };
assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT[27:11], LEDS };
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
......@@ -446,10 +446,10 @@ P9_41_42_IOPADS P9_41_42_IOPADS_0(
.P9_42 ( P9_42 )
);
blinky blink_0( // ①
snakey snakey_0( // ①
.clk ( PCLK ), // ②
.resetn ( PRESETN ), // ③
.blink ( BLINK ) // ④
.leds ( LEDS ) // ④
);
endmodule
`timescale 1ns/100ps
module blinky(
input clk,
input resetn,
output blink
module snakey(
input clk,
input resetn,
output [10:0] leds
);
wire tick = (counter == 5000000);
reg [24:0] counter = 0;
reg direction = 0;
reg [22:0] counter;
always@(posedge clk or negedge resetn) begin
if(~resetn) begin
leds <= 11'b00011111000;
direction <= ~direction;
counter <= 0;
end else begin
if (tick) begin
if (direction)
leds <= { leds[9:0], leds[10] };
else
leds <= { leds[0], leds[10:1] };
assign blink = counter[22];
always@(posedge clk or negedge resetn)
begin
if(~resetn)
begin
counter <= 16'h0000;
end
else
begin
counter <= counter + 1;
end
counter <= 0;
end else begin
counter <= counter + 1;
end
end
end
endmodule
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