- Mar 11, 2024
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Jason Kridner authored
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Jason Kridner authored
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Jason Kridner authored
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Vauban authored
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Vauban authored
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Jason Kridner authored
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Jason Kridner authored
Copy thoughts from https://openbeagle.org/lorforlinux/gpio-leds-gateware
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Jason Kridner authored
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Vauban authored
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Jason Kridner authored
This currently limits builds to just a single configuration, which misses the point of the other builder, but makes things drastically simpler. I think the feature of building all of the configurations within a build-options folder could be done much simpler than by cloning the repository a second time. Not using the installed copy of the repo causes headaches in building private repositories and generally serves to confuse and slow things down. Another issue is I don't know where the tests are run and report is generated. This is not preserved by this patch.
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Vauban authored
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Vauban authored
Adjust DDR drive strength and ODT settings to improve DDR training results.
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- Feb 25, 2024
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Vauban authored
Ensure version generated from date time is below 0xFFFF to prevent modulo 65536 of the generated value causing failure to work out the time at which the design was generated.
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- Feb 24, 2024
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Vauban authored
Remove the need to update the unique-design-version entry in the build option YAML file between builds to ensure successful FPGA programming. An FPGA design version based on the date and time is generated when no unique-design-version is specified simplifying interactive build/debug cycles.
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- Feb 13, 2024
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Jason Kridner authored
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Aven Arlington authored
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Aven Arlington authored
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- Feb 11, 2024
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Vauban authored
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- Jan 19, 2024
- Dec 28, 2023
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Vauban authored
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- Dec 26, 2023
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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- Dec 19, 2023
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Vauban authored
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- Dec 10, 2023
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Vauban authored
BeagleV-Fire uses the PolarFire-Soc IAP feature to reprogram the SoC-FPGA from Linux. The IAP mode used only actually programs the device if the Libero design version is different from the one in the currently programmed FPGA design. This change to the gateware builder uses the gateware repo's git hash to generate a Libero design version number which will be different with each push to a forked gateware repository. This results in the bitstream generated by the CI to successfully reprogram the SoC-FPGA after each change to the gateware source code.
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- Dec 09, 2023
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Vauban authored
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- Dec 04, 2023
- Dec 03, 2023
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Vauban authored
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- Nov 22, 2023
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Vauban authored
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- Nov 21, 2023
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Vauban authored
Set CI tag to libero-soc-v2023.2 to execute CI on gitlab runners using version 2023.2 of Libero.
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- Nov 20, 2023
- Nov 19, 2023
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Vauban authored
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Vauban authored
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Vauban authored
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Vauban authored
Correct the location of the gateware source code in the script that generates the device tree overlay for the gateware.
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Vauban authored
The build configuration YAML files describing a custom gateware configuration will be used by the CI system generate bitstreams for user custom FPGA designs.
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Vauban authored
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- Nov 11, 2023