index.rst

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.. _gsoc-project-ideas:

Ideas
######

.. image:: ../_static/images/ideas-below.webp
   :align: center

.. admonition:: How to participate?

   Contributors are expected to go through the list of ideas dropdown below and join the discussion by clicking on the
   ``Discuss on forum`` button. All ideas have colorful badges for ``Complexity`` and
   ``Size`` for making the selection process easier for contributors. Anyone is welcome to
   introduce new ideas via the `forum gsoc-ideas tag <https://forum.beagleboard.org/tag/gsoc-ideas>`_.
   Only ideas with sufficiently experienced mentor backing as deemed by the administrators will
   be added here.

   +------------------------------------+-------------------------------+
   | Complexity                         | Size                          |
   +====================================+===============================+
   | :bdg-danger:`High complexity`      | :bdg-danger-line:`350 hours`  |
   +------------------------------------+-------------------------------+
   | :bdg-success:`Medium complexity`   | :bdg-success-line:`175 hours` |
   +------------------------------------+-------------------------------+
   | :bdg-info:`Low complexity`         | :bdg-info-line:`90 hours`     |
   +------------------------------------+-------------------------------+

.. card:: Low-latency I/O RISC-V CPU core in FPGA fabric

   :fas:`microchip;pst-color-primary` FPGA gateware improvements :bdg-success:`Medium complexity` :bdg-success-line:`175 hours`

   ^^^^

   BeagleV-Fire features RISC-V 64-bit CPU cores and FPGA fabric. In that FPGA fabric, we'd like to
   implement a RISC-V 32-bit CPU core with operations optimized for low-latency GPIO. This is similar
   to the programmable real-time unit (PRU) RISC cores popularized on BeagleBone Black.

   | **Goal:** RISC-V-based CPU on BeagleV-Fire FPGA fabric with GPIO
   | **Hardware Skills:** `Verilog`_, `verification`_, `FPGA`_
   | **Software Skills:** `RISC-V ISA`_, `assembly`_, `Linux`_
   | **Possible Mentors:** `Cyril Jean <https://forum.beagleboard.org/u/vauban>`_, `Jason Kridner <https://forum.beagleboard.org/u/jkridner>`_

   ++++

   .. button-link:: https://forum.beagleboard.org/t/low-latency-risc-v-i-o-cpu-core/37156
      :color: danger
      :expand:

      :fab:`discourse;pst-color-light` Discuss on forum


.. card:: Update beagle-tester for mainline testing

   :fab:`linux;pst-color-primary` Linux kernel improvements :bdg-success:`Medium complexity` :bdg-danger-line:`350 hours`

   ^^^^

   Utilize the ``beagle-tester`` application and ``Buildroot`` along with device-tree and udev symlink concepts within
   the OpenBeagle continuous integration server context to create a regression test suite for the Linux kernel
   and device-tree overlays on various Beagle computers.

   | **Goal:** Execution on Beagle test farm with over 30 mikroBUS boards testing all mikroBUS enabled cape interfaces (PWM, ADC, UART, I2C, SPI, GPIO and interrupt) performing weekly mainline Linux regression verification
   | **Hardware Skills:** `basic wiring`_, `embedded serial interfaces`_
   | **Software Skills:** `device-tree`_, `Linux`_, `C`_, `OpenBeagle CI`_, `Buildroot`_
   | **Possible Mentors:** `Deepak Khatri <https://forum.beagleboard.org/u/lorforlinux>`_, `Anuj Deshpande <https://forum.beagleboard.org/u/Anuj_Deshpande>`_, `Dhruva Gole <https://forum.beagleboard.org/u/dhruvag2000>`_

   ++++

   .. button-link:: https://forum.beagleboard.org/t/update-beagle-tester-for-cape-mikrobus-new-board-and-upstream-testing/37279
      :color: danger
      :expand:

      :fab:`discourse;pst-color-light` Discuss on forum

.. card:: Upstream wpanusb and bcfserial

   :fab:`linux;pst-color-primary` Linux kernel improvements :bdg-success:`Medium complexity` :bdg-success-line:`175 hours`
   
   ^^^^

   These are the drivers that are used to enable Linux to use a BeagleConnect Freedom as a SubGHz IEEE802.15.4 radio (gateway).
   They need to be part of upstream Linux to simplify on-going support. There are several gaps that are known before they are
   acceptable upstream.

   | **Goal:** Add functional gaps, submit upstream patches for these drivers and respond to feedback
   | **Hardware Skills:** `wireless communications`_
   | **Software Skills:** `C`_, `Linux`_
   | **Possible Mentors:** `Ayush Singh <https://forum.beagleboard.org/u/ayush1325>`_, `Jason Kridner <https://forum.beagleboard.org/u/jkridner>`_

   ++++

   .. button-link:: https://forum.beagleboard.org/t/upstream-wpanusb-and-bcfserial/37186
      :color: danger
      :expand:

      :fab:`discourse;pst-color-light` Discuss on forum

.. card:: ``librobotcontrol`` support for newer boards

   :fas:`wand-sparkles;pst-color-danger` Automation and industrial I/O :bdg-success:`Medium complexity` :bdg-success-line:`175 hours`

   ^^^^

   Preliminary librobotcontrol support for BeagleBone AI, BeagleBone AI-64 and BeagleV-Fire has been drafted, but it
   needs to be cleaned up. We can also work on support for Raspberry Pi if UCSD releases their Hat for it.

   | **Goal:** Update librobotcontrol for Robotics Cape on BeagleBone AI, BeagleBone AI-64 and BeagleV-Fire
   | **Hardware Skills:** `basic wiring`_, `motors`_
   | **Software Skills:** `C`_, `Linux`_
   | **Possible Mentors:** `Deepak Khatri <https://forum.beagleboard.org/u/lorforlinux>`_, `Jason Kridner <https://forum.beagleboard.org/u/jkridner>`_
   
   ++++

   .. button-link:: https://forum.beagleboard.org/t/librobotcontrol-support-for-newer-boards/37187
      :color: danger
      :expand:

      :fab:`discourse;pst-color-light` Discuss on forum

.. card:: Upstream Zephyr Support on BBAI-64 R5

   :fas:`timeline;pst-color-secondary` RTOS/microkernel imporvements :bdg-success:`Medium complexity` :bdg-success-line:`350 hours`
   
   ^^^^

   Incorporating Zephyr RTOS support onto the Cortex-R5 cores of the TDA4VM SoC along with Linux operation on the A72 core. The objective is to harness the combined capabilities of both systems
   to support BeagleBone AI-64.

   | **Goal:** submit upstream patches to support BeagleBone AI-64 and respond to feedback
   | **Hardware Skills:** Familiarity with ARM Cortex R5
   | **Software Skills:** `C`_, `RTOS  <https://docs.zephyrproject.org/latest/develop/getting_started/index.html>`_
   | **Possible Mentors:** `Dhruva Gole <https://forum.beagleboard.org/u/dhruvag2000>`_, `Nishanth Menon <https://forum.beagleboard.org/u/nishanth_menon>`_
   | **Upstream Repository:** `The primary repository for Zephyr Project <https://github.com/zephyrproject-rtos/zephyr>`_

   ++++

   .. button-link:: https://forum.beagleboard.org/t/upstream-zephyr-support-on-bbai-64-r5/37294/1
      :color: danger
      :expand:

      :fab:`discourse;pst-color-light` Discuss on forum

.. card:: Enhanced Media Experience with AI-Powered Commercial Detection and Replacement

   :fas:`brain;pst-color-secondary` Deep Learning :bdg-success:`Medium complexity` :bdg-success-line:`350 hours`
   
   ^^^^

   Leveraging the capabilities of BeagleBoard’s powerful processing units, the project will focus on creating a real-time, efficient solution that enhances media consumption experiences by seamlessly integrating custom audio streams during commercial breaks.

   | **Goal:** Build a deep learning model, training data set, training scripts, and a runtime for detection and modification of the video stream.
   | **Hardware Skills:** Ability to capture and display video streams using `BeagleBone AI-64 <https://www.beagleboard.org/boards/beaglebone-ai-64>`_
   | **Software Skills:** `Python <https://www.python.org/>`_, `TensorFlow <https://www.tensorflow.org/>`_, `TFlite <https://www.tensorflow.org/lite>`_, `Keras <https://www.tensorflow.org/guide/keras>`_, `GStreamer <https://gstreamer.freedesktop.org/>`_, `OpenCV <https://opencv.org/>`_
   | **Possible Mentors:** `Jason Kridner <https://forum.beagleboard.org/u/jkridner>`_, `Deepak Khatri <https://forum.beagleboard.org/u/lorforlinux>`_

   ++++

.. card:: Embedded differentiable logic gate networks for real-time interactive and creative applications

   :fas:`brain;pst-color-secondary` Creative AI :bdg-success:`Medium complexity` :bdg-success-line:`350 hours`
   
   ^^^^

   This project seeks to explore the potential of creative embedded AI, specifically using `Differentiable Logic (DiffLogic) <https://github.com/Felix-Petersen/difflogic>`_, by creating a system that can perform tasks like machine listening, sensor processing, sound and gesture classification, and generative AI.

   | **Goal:** Develop an embedded machine learning system on BeagleBone that leverages `Differentiable Logic (DiffLogic) <https://github.com/Felix-Petersen/difflogic>`_ for real-time interactive music creation and environment sensing. 
   | **Hardware Skills:** Audio and sensor IO with `Bela.io <http://bela.io>`_
   | **Software Skills:** Machine learning, deep learning, BeagleBone Programmable Real Time Unit (PRU) programming (see `PRU Cookbook <https://docs.beagleboard.org/latest/books/pru-cookbook/index.html>`_).
   | **Possible Mentors:** `Jack Armitage <https://forum.beagleboard.org/u/jarm>`_, `Chris Kiefer <https://forum.beagleboard.org/u/luuma>`_

   ++++

   .. button-link:: https://forum.beagleboard.org/t/enhanced-media-experience-with-ai-powered-commercial-detection-and-replacement/37358
      :color: danger
      :expand:

      :fab:`discourse;pst-color-light` Discuss on forum

.. button-link:: https://forum.beagleboard.org/tag/gsoc-ideas
   :color: danger
   :expand:
   :outline:

   :fab:`discourse;pst-color-light` Visit our forum to see newer ideas being discussed!


.. tip::
   
   You can also check our our :ref:`gsoc-old-ideas` and :ref:`Past_Projects` for inspiration.

.. _C:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/c.html

.. _Assembly:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/assembly.html

.. _Verilog:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/verilog.html

.. _Zephyr:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/zephyr.html

.. _Linux:
   https://docs.beagleboard.org/latest/intro/beagle101/linux.html

.. _device-tree:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/device-tree.html

.. _FPGA:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/fpga.html

.. _basic wiring:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/basic-wiring.html

.. _motors:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/motors.html

.. _embedded serial interfaces:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/embedded-serial.html

.. _OpenBeagle CI:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/openbeagle-ci.html

.. _verification:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/verification.html

.. _wireless communications:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/wireless-communications.html

.. _Buildroot:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/buildroot.html

.. _RISC-V ISA:
   https://jkridner.beagleboard.io/docs/latest/intro/beagle101/riscv.html