[Minor Changes]: Adds links to repositories and update threads

This PR adds the links to update forum threads, code-in and upstream repositories to the proposal.

proposals/RISC-V_CPU_core_in_FPGA_fabric.rst

@@ -17,6 +17,7 @@ Summary links
 - - *Upstream Repository:* `BeagleV-Fire gateware <https://openbeagle.org/beaglev-fire/gateware>`_
 - - *Daily Code Check-in Repository:* `Fork for BeagleV-Fire gateware <https://openbeagle.org/Roger18/gateware>`_
 - **Weekly/biweekly Updates Forums Thread:** `Progress Reports <https://forum.beagleboard.org/t/weekly-progress-report-low-latency-i-o-risc-v-cpu-core-in-fpga-fabric/38488>`_
+- **Blog:** `TechTales <https://rapidroger18.github.io/>`_
 
 Status
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@@ -65,9 +66,9 @@ Based on the requirements of the project, it is most efficient to use PicoRV (an
 This problem will be resolved within the first stage of the project, which will focus on making the core I/O compatible and modifying its execution flow to ensure single-cycle execution for all instructions. Some present soft processor IPs like AMD’s Microblaze used in Vivado Design Suite and Microchip’s Mi-V used in Libero Design suite can provide good insights on how a functioning soft core IP will look like.
 As the Stage-1 of this project concludes with deployment of the RV core, Stage-2 will focus on establishing a communication medium between the PRU and the main CPU. This will ensure the ‘on-the-fly’ programming for the PRU and high bandwidth data transfer from I/O to the main CPU.
 
-riscv64-unknown-elf-gcc compiler will compile the C program into bare-metal RISC-V based binary instructions within the linux booted on the main CPU. The communication between main CPU and PRU will be used to send these instructions into the program memory of PRU without needing to flash the FPGA each time.
+*riscv64-unknown-elf-gcc* compiler will compile the C program into bare-metal RISC-V based binary instructions within the linux booted on the main CPU. The communication between main CPU and PRU will be used to send these instructions into the program memory of PRU without needing to flash the FPGA each time.
 
- This connection can be established in multiple ways: 
+This connection can be established in multiple ways: 
 
 1. The Program Memory of the PRU can be written into SPI flash that contains FPGA logic, and the data transfer will take place through 32-bit interconnecting AXI bus.
 2. Shared memory between PRU and Main CPU can be used of PRU memory and Data Transfer.