[Minor Changes]: Adds links to repositories and update threads
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@@ -17,6 +17,7 @@ Summary links
@@ -65,9 +66,9 @@ Based on the requirements of the project, it is most efficient to use PicoRV (an
This problem will be resolved within the first stage of the project, which will focus on making the core I/O compatible and modifying its execution flow to ensure single-cycle execution for all instructions. Some present soft processor IPs like AMD’s Microblaze used in Vivado Design Suite and Microchip’s Mi-V used in Libero Design suite can provide good insights on how a functioning soft core IP will look like.
riscv64-unknown-elf-gcc compiler will compile the C program into bare-metal RISC-V based binary instructions within the linux booted on the main CPU. The communication between main CPU and PRU will be used to send these instructions into the program memory of PRU without needing to flash the FPGA each time.
*riscv64-unknown-elf-gcc* compiler will compile the C program into bare-metal RISC-V based binary instructions within the linux booted on the main CPU. The communication between main CPU and PRU will be used to send these instructions into the program memory of PRU without needing to flash the FPGA each time.