How can I make OBSCLK0 output 25Mhz clock?
I am trying to make the ETH PHY chip(DP83867) work with the clock generated by the AM67's OBSCLK0 pin(A10/MCU_OBSCLK0/3V3).
And I tried to enable the OBSCLK0 in k3-j722s-evm.dts with the following patch:
diff --git a/src/arm64/ti/k3-j722s-evm.dts b/src/arm64/ti/k3-j722s-evm.dts
index b0437a3f..a7622444 100644
--- a/src/arm64/ti/k3-j722s-evm.dts
+++ b/src/arm64/ti/k3-j722s-evm.dts
@@ -734,6 +734,12 @@
J722S_MCU_IOPAD(0x0030, PIN_OUTPUT, 7) /* (C3) WKUP_UART0_RTSn.MCU_GPIO0_12 */
>;
};
+
+ gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins {
+ pinctrl-single,pins = <
+ J722S_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (A10) MCU_SPI0_CS1.MCU_OBSCLK0 */
+ >;
+ };
};
&wkup_uart0 {
@@ -966,7 +972,7 @@ csi0_i2c: &main_i2c2 {
&cpsw3g {
status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default>;
+ pinctrl-0 = <&rgmii1_pins_default>, <&gbe_pmx_obsclk>;
};
With this patch I can get the OBSCLK0 output a clock of about 12Mhz, which is not I wanted.
What should I do to make this clock 25Mhz?