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Commit 91213647 authored by Lars Randers's avatar Lars Randers Committed by Vauban
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Cape: dtso: prepare for kernel-next (3/3) 

- Adapt to unified driver
parent d6312704
Branches
1 merge request!116Cape: dtso: prepare for kernel-next
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with 17 additions and 17 deletions
sources/FPGA-design/script_support/components/CAPE/4_UARTS/device-tree-overlay/cape-gpios.dtso
+ 2
− 2
View file @ 91213647
......@@ -24,7 +24,7 @@
};
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio","microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......@@ -38,7 +38,7 @@
};
cape_gpios_p9: gpio@41200000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41200000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......
sources/FPGA-design/script_support/components/CAPE/CLICK_BOARDS/device-tree-overlay/cape-gpios.dtso
+ 2
− 2
View file @ 91213647
......@@ -24,7 +24,7 @@
};
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......@@ -38,7 +38,7 @@
};
cape_gpios_p9: gpio@41200000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41200000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......
sources/FPGA-design/script_support/components/CAPE/COMMS_CAPE/device-tree-overlay/comms-cape.dtso
+ 2
− 2
View file @ 91213647
......@@ -24,7 +24,7 @@
};
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......@@ -38,7 +38,7 @@
};
cape_gpios_p9: gpio@41200000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41200000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......
sources/FPGA-design/script_support/components/CAPE/DEFAULT/device-tree-overlay/cape-gpios.dtso
+ 2
− 2
View file @ 91213647
......@@ -24,7 +24,7 @@
};
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......@@ -38,7 +38,7 @@
};
cape_gpios_p9: gpio@41200000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41200000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......
sources/FPGA-design/script_support/components/CAPE/GPIOS/device-tree-overlay/cape-gpios.dtso
+ 2
− 2
View file @ 91213647
......@@ -15,7 +15,7 @@
#size-cells = <2>;
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......@@ -29,7 +29,7 @@
};
cape_gpios_p9: gpio@41200000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41200000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......
sources/FPGA-design/script_support/components/CAPE/ROBOTICS/device-tree-overlay/robotics-cape.dtso
+ 2
− 2
View file @ 91213647
......@@ -15,7 +15,7 @@
#size-cells = <2>;
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
interrupt-parent = <&plic>;
......@@ -35,7 +35,7 @@
};
cape_gpios_p9: gpio@41200000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41200000 0x0 0x1000>;
clocks = <&fabric_clk3>;
interrupt-parent = <&plic>;
......
sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/device-tree-overlay/verilog-cape.dtso
+ 1
− 1
View file @ 91213647
......@@ -15,7 +15,7 @@
#size-cells = <2>;
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
interrupt-parent = <&plic>;
......
sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/device-tree-overlay/verilog-cape.dtso
+ 1
− 1
View file @ 91213647
......@@ -15,7 +15,7 @@
#size-cells = <2>;
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
interrupt-parent = <&plic>;
......
sources/FPGA-design/script_support/components/M2/BOARD_TESTS/device-tree-overlay/pcie.dtso
+ 1
− 1
View file @ 91213647
......@@ -16,7 +16,7 @@
#size-cells = <2>;
m2_test_gpios: gpio@43000000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x43000000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......
sources/FPGA-design/script_support/components/SYZYGY/BOARD_TESTS_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso
+ 1
− 1
View file @ 91213647
......@@ -15,7 +15,7 @@
#size-cells = <2>;
hsi_gpios: gpio@44000000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x44000000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......
sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/device-tree-overlay/syzygy-test-gpios.dtso
+ 1
− 1
View file @ 91213647
......@@ -13,7 +13,7 @@
&{/} {
fabric-bus@40000000 {
hsi_gpios: gpio@44000000 {
compatible = "microchip,core-gpio";
compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
reg = <0x0 0x44000000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
......
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