Board: Selection of board using argument - base layout for MPFS-ICICLE-KIT-ES is provided

MSS .cfg, constraint and dtso files now selected dynamically based on BOARD DIE PACKAGE

PART_VOLTAGE and DIE_VOLTAGE arguments can be passed if they differ from the default

BVF is selected by default if no BOARD argument defined

Signed-off-by: Brian Burke <Brian.Burke@microchip.com>

gateware_scripts/build_gateware.py

@@ -44,6 +44,7 @@ import sys
 import subprocess
 import datetime
 import glob
+import glob
 
 from gateware_scripts.generate_gateware_overlays import generate_gateware_overlays
 from gateware_scripts.Logger import Logger
@@ -477,6 +478,9 @@ def build_gateware(yaml_input_file_path, build_dir, gateware_top_dir, board_opti
 
     sources = clone_sources(yaml_input_file)
 
+    with open(yaml_input_file_path, 'r') as file:
+        yaml_content = yaml.safe_load(file)
+
     build_options_list = get_libero_script_args(yaml_input_file)
     generate_gateware_overlays(os.path.join(gateware_top_dir, "sources", "FPGA-design"),
                                os.path.join(os.getcwd(), "bitstream", "LinuxProgramming"), build_options_list)

sources/FPGA-design/BUILD_BVF_GATEWARE.tcl

@@ -115,12 +115,20 @@ if {[info exists MIPI_CSI_OPTION]} {
 }
 puts "MIPI CSI option option selected: $mipi_csi_option"
 
+if {[info exists MSS_CFG]} {
+    set mss_cfg_option "$MSS_CFG"
+} else {
+    set mss_cfg_option "MSS_LINUX"
+}
+puts "MSS_CFG option selected: $mss_cfg_option"
+
 if {[info exists PROJECT_LOCATION]} {
     set project_dir "$PROJECT_LOCATION"
 } else {
     set project_dir "$local_dir/$project_name"
 }
 puts "PROJECT_LOCATION: $project_dir"
+puts "PROJECT_LOCATION: $project_dir"
 
 if {[info exists DESIGN_VERSION]} {
     set gateware_design_version "$DESIGN_VERSION"
@@ -128,6 +136,7 @@ if {[info exists DESIGN_VERSION]} {
     set gateware_design_version "1"
 }
 puts "DESIGN_VERSION: $gateware_design_version"
+puts "DESIGN_VERSION: $gateware_design_version"
 
 if {[info exists SILICON_SIGNATURE]} {
     set gateware_silicon_signature "$SILICON_SIGNATURE"
@@ -195,9 +204,13 @@ new_project \
     -family {PolarFireSoC} \
     -die $die \
     -package $package \
+    -die $die \
+    -package $package \
     -speed {STD} \
     -die_voltage $die_voltage \
     -part_range $part_range \
+    -die_voltage $die_voltage \
+    -part_range $part_range \
     -adv_options {IO_DEFT_STD:LVCMOS 1.8V} \
     -adv_options {RESTRICTPROBEPINS:0} \
     -adv_options {RESTRICTSPIPINS:0} \

sources/FPGA-design/script_support/constraints/mpfs-icicle-kit-es/MPFS250T_ES/FCVG484/base_design.pdc

-set_iobank -bank_name Bank1  \
-    -vcci 3.30               \
-    -fixed true             \
-    -update_iostd true
-
-
-set_io -port_name PHY_RSTn	\
-    -pin_name U18	\
-    -fixed true	\
-    -DIRECTION INOUT
-
-
-set_io -port_name PHY_INTn	\
-    -pin_name V12	\
-    -fixed true	\
-    -DIRECTION INOUT
-
-
-set_io -port_name ADC_MCLK	\
-    -pin_name E19	\
-    -fixed true	\
-    -io_std LVCMOS33  \
-    -DIRECTION OUT
-
-set_io -port_name USB0_RESETB \
-    -pin_name Y19 \
-    -fixed true \
-    -DIRECTION OUTPUT
-
-set_io -port_name VIO_ENABLE \
-    -pin_name V16 \
-    -fixed true \
-    -DIRECTION OUTPUT
-
-set_io -port_name M2_W_DISABLE1  \
-    -pin_name U19                \
-    -fixed true                  \
-    -DIRECTION OUTPUT
-
-set_io -port_name M2_W_DISABLE2  \
-    -pin_name R15                \
-    -fixed true                  \
-    -DIRECTION OUTPUT
-
-set_io -port_name P9_19 \
-    -pin_name A10	\
-    -fixed true	\
-    -io_std LVCMOS33  \
-    -DIRECTION INOUT    
-
-set_io -port_name P9_20	\
-    -pin_name A11	\
-    -fixed true	\
-    -io_std LVCMOS33  \
-    -DIRECTION INOUT
-
-set_io -port_name SD_DET  \
-    -pin_name C7          \
-    -fixed true           \
-    -io_std LVCMOS33      \
-    -DIRECTION INPUT