Cape: Default: Correct MISO/MOSI signals.

sources/FPGA-design/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl

@@ -32,6 +32,8 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN14} -port_direction
 sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN16} -port_direction {OUT}
 sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN42} -port_direction {OUT}
 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_29} -port_direction {IN} 
+
 #-------------------------------------------------------------------------------
 # Instantiate.
 #-------------------------------------------------------------------------------
@@ -88,17 +90,16 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_
 sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_SS1} -port_name {} 
 sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_CLK} -port_name {} 
 sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_DO} -port_name {} 
-sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_DI} -new_port_name {P9_18} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_DI} -new_port_name {P9_21} 
 sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_CLK} -new_port_name {P9_22} 
-sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_DO} -new_port_name {P9_21} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_DO} -new_port_name {P9_18} 
 sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_SS1} -new_port_name {P9_17} 
 
 sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_SS1} 
 sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_CLK} 
-sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_DO} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_DO} -port_name {} 
 sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_SS1} -port_name {} 
 sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_CLK} -port_name {} 
 sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_SS1} -new_port_name {P9_28} 
 sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_CLK} -new_port_name {P9_31} 
-sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_DO} -new_port_name {P9_29} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:SPI_1_DI" "P9_29"}

sources/FPGA-design/script_support/components/CAPE/DEFAULT/Readme.md

@@ -72,10 +72,10 @@
 | P9_15  | core_gpio[4] @ 0x41200000  |  146  | GPIO        |
 | P9_16  | core_pwm[1] @ 0x41400000   |  n/a  | PWM_1:1     |
 | P9_17  | MSS SPI0                   |   54  | SPI0 CS     |
-| P9_18  | MSS SPI0                   |   54  | SPI0 DI     |
+| P9_18  | MSS SPI0                   |   54  | SPI0 MOSI   |
 | P9_19  | MSS I2C0                   |   58  | I2C0 SCL    |
 | P9_20  | MSS I2C0                   |   58  | I2C0 SDA    |
-| P9_21  | MSS SPI0                   |   54  | SPI0 DO     |
+| P9_21  | MSS SPI0                   |   54  | SPI0 MISO   |
 | P9_22  | MSS SPI0                   |   54  | SPI0 SCLK   |
 | P9_23  | core_gpio[10] @ 0x41200000 |  152  | GPIO        |
 | P9_24  | MMUART2                    |   92  | UART1 TX    |
@@ -83,7 +83,7 @@
 | P9_26  | MMUART2                    |   92  | UART2 RX    |
 | P9_27  | core_gpio[14] @ 0x41200000 |  156  | GPIO        |
 | P9_28  | MSS SPI1                   |   55  | SPI1 CS     |
-| P9_29  | MSS SPI1                   |   55  | SPI1 DO     |
+| P9_29  | MSS SPI1                   |   55  | SPI1 MISO   |
 | P9_30  | core_gpio[17] @ 0x41200000 |  159  | GPIO        |
 | P9_31  | MSS SPI1                   |   55  | SPI1 SCLK   |
 | P9_32  | n/a                        |  n/a  | VDD ADC     |

sources/FPGA-design/script_support/components/CAPE/DEFAULT/constraints/cape.pdc

@@ -39,24 +39,27 @@ set_io -port_name P9_17	\
     -pin_name C9	\
     -fixed true	\
     -io_std LVCMOS33  \
+    -OUT_DRIVE 16        \
     -DIRECTION OUTPUT
 
 set_io -port_name P9_18	\
     -pin_name C10	\
     -fixed true	\
     -io_std LVCMOS33  \
-    -DIRECTION INPUT
+    -OUT_DRIVE 16        \
+    -DIRECTION OUTPUT
 
 set_io -port_name P9_21	\
     -pin_name B8	\
     -fixed true	\
     -io_std LVCMOS33  \
-    -DIRECTION OUTPUT
+    -DIRECTION INPUT
 
 set_io -port_name P9_22	\
     -pin_name A8	\
     -fixed true	\
     -io_std LVCMOS33  \
+    -OUT_DRIVE 16        \
     -DIRECTION OUTPUT
 
 
@@ -94,13 +97,14 @@ set_io -port_name P9_28	\
     -pin_name C11	\
     -fixed true	\
     -io_std LVCMOS33  \
+    -OUT_DRIVE 16        \
     -DIRECTION OUTPUT
 
 set_io -port_name P9_29	\
     -pin_name F17	\
     -fixed true	\
     -io_std LVCMOS33  \
-    -DIRECTION OUTPUT
+    -DIRECTION INPUT
 
 set_io -port_name P9_PIN30	\
     -pin_name F16	\
@@ -112,6 +116,7 @@ set_io -port_name P9_31	\
     -pin_name E18	\
     -fixed true	\
     -io_std LVCMOS33  \
+    -OUT_DRIVE 16        \
     -DIRECTION OUTPUT
 
 set_io -port_name P9_PIN41	\