- Dec 31, 2024
-
-
Manish V Badarkhe authored
-
Manish V Badarkhe authored
-
Manish Pandey authored
* changes: feat(mbedtls): optimize SHA256 for reduced memory footprint refactor(arm): rename ARM_ROTPK_HEADER_LEN docs(arm): update docs to reflect rotpk key changes feat(arm): use provided algs for (swd/p)rotpk feat(arm): use the provided hash alg to hash rotpk
-
Maxime Méré authored
By default, the ECDSA Brainpool regular and ECDSA Brainpool twisted algorithms support 256-bit sized keys. Not defining this leads to an error indicating that '256' is not a valid key size for ECDSA Brainpool. KEY_SIZES matrix must have a value in its table to avoid problems when KEY_SIZE is defined. Signed-off-by:
Maxime Méré <maxime.mere@foss.st.com> Change-Id: I34886659315f59a9582dcee1d92d0e24d4a4138e
-
- Dec 30, 2024
-
-
Manish V Badarkhe authored
Set MBEDTLS_SHA256_SMALLER as the default mbedTLS configuration to minimize memory usage, trading off some processing speed for a smaller footprint. Change-Id: Ibfa6e115a0ed94096b9acdd9e237f3fb5457071d Signed-off-by:
Manish V Badarkhe <Manish.Badarkhe@arm.com>
-
Ryan Everett authored
This variable had a misleading name, as it is the length of the header only when the ROTPK is a hash. Also rename arm_rotpk_header to match the new pattern. Change-Id: I36c29998eebf50c356a6ca959ec9223c8837b540 Signed-off-by:
Ryan Everett <ryan.everett@arm.com>
-
Ryan Everett authored
The hashing algorithm for the rotpk is now HASH_ALG, not always sha-256. The public development keys are no longer in the repository and are now generated at run-time, updates the documentation to reflect this. Change-Id: Ic336f7aca858e9b6a1af6d6e6dc5f4aa428da179 Signed-off-by:
Ryan Everett <ryan.everett@arm.com>
-
Ryan Everett authored
No longer hard code SHA-256 hashed rsa dev keys, now the keys can use pair of key alg: rsa, p256, p384 and hash alg: sha256, sha384, sha512. All public keys are now generated at build-time from the dev keys. Change-Id: I669438b7d1cd319962c4a135bb0e204e44d7447e Signed-off-by:
Ryan Everett <ryan.everett@arm.com>
-
Ryan Everett authored
No longer hard code SHA-256 hashed dev rotpks, instead use the algorithm given by HASH_ALG. This means that we no longer need the plat_arm_configs (once the protpk and swd_rotpk are also updated to use HASH_ALG). The rot public key is now generated at build time, as is the header for the key. Also support some default 3k and 4k RSA keys. Change-Id: I33538124aeb4fa7d67918d878d17f2a84d3a6756 Signed-off-by:
Ryan Everett <ryan.everett@arm.com>
-
- Dec 24, 2024
-
-
Manish Pandey authored
* changes: feat(mt8196): enable APU on mt8196 feat(mt8196): add APU SMMU hardware semaphore operations feat(mt8196): add smpu protection for APU secure memory feat(mt8196): add APU RCX DevAPC setting feat(mt8196): add APU kernel control operations feat(mt8196): add APU power on/off functions feat(mt8196): add APUMMU setting feat(mt8196): enable apusys mailbox mpu protection feat(mt8196): enable apusys security control feat(mt8196): add APUSYS AO DevAPC setting feat(mt8196): add APU power-on init flow
-
- Dec 23, 2024
-
-
Bipin Ravi authored
-
Manish Pandey authored
-
Jaiprakash Singh authored
Add Jaiprakash Singh as marvell maintainer Change-Id: Ica924c0502b0a271b0368255841ef413391de959 Signed-off-by:
Jaiprakash Singh <jaiprakashs@marvell.com>
-
Joanna Farley authored
* changes: fix(versal2): typecast operands to match data type fix(versal): typecast operands to match data type fix(versal-net): typecast operands to match data type fix(xilinx): typecast operands to match data type fix(zynqmp): typecast operands to match data type fix(versal-net): typecast operands to match data type fix(versal): typecast operands to match data type fix(xilinx): typecast operands to match data type fix(zynqmp): typecast operands to match data type fix(versal2): typecast expressions to match data type fix(versal-net): typecast expressions to match data type fix(versal): typecast expressions to match data type fix(xilinx): typecast expressions to match data type fix(zynqmp): typecast expressions to match data type fix(zynqmp): align essential type categories fix(zynqmp): typecast expression to match data type fix(xilinx): typecast expression to match data type
-
Sammit Joshi authored
Commit a6485b2b ("refactor(delay-timer): add timer callback functions") introduced a requirement for timer-related APIs to have a timer object initialized before use. This caused assertion failures in SMMU routines on Neoverse platforms, as they relied on timer APIs. Resolve this issue by initializing the timer early during platform boot to set up the timer_ops object properly. Change-Id: I3d9ababdb7897185f23e9ccf982b9aab6c666b8c Signed-off-by:
Sammit Joshi <sammit.joshi@arm.com>
-
- Dec 20, 2024
-
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I37ec9f8d716347df9acea5eb084f5a423a32a058 Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: Ie82297e7eb5faa5d45b1a613c59516052e0c5ecb Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: Ie2d32d5554d251cde8a9c8b7c7a85666ea505a15 Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I1606422aadfd64b283fd9948b6dadcddecdf61e0 Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.3: The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I141fbc554265173df0ca90c2ddc7f28137c6b0f1 Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.1: Operands shall not be of an inappropriate essential type. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: If0a6ffa84c4d1ce5ae08337a4eb20c9a221d7795 Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.1: Operands shall not be of an inappropriate essential type. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I41b08349fc6023458ffc6e126f58293a9ef37422 Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.1: Operands shall not be of an inappropriate essential type. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I675f1b2ac408b70a9ca307fb5161ebb8e597897c Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.1: Operands shall not be of an inappropriate essential type. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I016f9df3811d80cd230257b5533d4d15a15fe14f Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.4: Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: Ia352e3cf261b52777c1c431701e1e6c3be9cd279 Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.4: Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I5add78285ff0e48aa6c0fb639e7e2924f5bf9000 Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.4: Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: Ide520aa8ec900d0e23e80753d7082e34b6897e8f Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.4: Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I9110ea86f5ee49af0b21be78fd0890742ef95ddf Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.4: Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: I847af07f5e4f139384c1ed50bee765b892a6e9cd Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.7: If a composite expression is used as one operand of an operator in which the usual arithmetic conversions are performed then the other operand shall not have wider essential type. Explicitly type casted to match the data type of both the operands. Change-Id: I670304682cc4945b8575f125ac750d0dc69079a7 Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.6: The value of a composite expression shall not be assigned to an object with wider essential type. Explicitly type casted to match the data type of composite expression. Change-Id: I6497453f9f7455ae2f1ad8a18760ff0ef41d7c40 Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Maheedhar Bollapalli authored
This corrects the MISRA violation C2012-10.6: The value of a composite expression shall not be assigned to an object with wider essential type. Explicitly type casted to match the data type of composite expression. Change-Id: I0fd845496b4d6ac702027eb2075a23b15849f7d6 Signed-off-by:
Nithin G <nithing@amd.com> Signed-off-by:
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
-
Olivier Deprez authored
-
- Dec 19, 2024
-
-
Manish V Badarkhe authored
* changes: feat(tc): add MCN PMU nodes in dts for TC4 feat(tc): add 'kaslr-seed' node in device tree for TC3 feat(tc): enable MCN non-secure access to pmu counters on TC4 feat(tc): define MCN related macros for TC4
-
Manish Pandey authored
-
Manish Pandey authored
-
Manish Pandey authored
-
Manish Pandey authored
-
Manish Pandey authored
* changes: fix(trbe): add a tsb before context switching fix(spe): add a psb before updating context and remove context saving
-
Jagdish Gediya authored
Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in kernel with perf. Signed-off-by:
Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by:
Icen Zeyada <Icen.Zeyada2@arm.com> Change-Id: I1a85ba646604336ce3f16c28171589af78f65251
-