* changes:
  style(fwu): change the metadata fields to align with specification
  style(partition): use GUID values for GPT partition fields
  feat(st): add logic to boot the platform from an alternate bank
  feat(st): add a function to clear the FWU trial state counter
  feat(fwu): add a function to obtain an alternate FWU bank to boot
  feat(fwu): add some sanity checks for the FWU metadata
  feat(fwu): modify the check for getting the FWU bank's state
  feat(st): get the state of the active bank directly
  feat(fwu): add a config flag for including image info in the FWU metadata
  feat(fwu): migrate FWU metadata structure to version 2
  feat(fwu): document the config flag for including image info in the FWU metadata
  feat(fwu): update the URL links for the FWU specification

* changes:
  refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
  refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
  refactor(sgi): move apis and types to "nrd" prefix
  refactor(sgi): replace build-option prefix to "NRD"
  refactor(sgi): move neoverse_rd out of css
  refactor(sgi): move from "sgi" to "neoverse_rd"
  feat(sgi): remove unused SGI_PLAT build-option
  fix(sgi): align to misra rule for braces
  feat(rde1edge): remove support for RD-E1-Edge
  fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled
  fix(board): update spi_id max for sgi multichip platforms

* changes:
  feat(smmu): separate out smmuv3_security_init from smmuv3_init
  feat(smmu): fix to perform INV_ALL before enabling GPC

* changes:
  docs(maintainers): add the maintainers for imx8ulp
  docs(imx8ulp): add imx8ulp platform
  fix(imx8ulp): increase the mmap region num
  feat(imx8ulp): adjust the dram mapped region
  feat(imx8ulp): ddrc switch auto low power and software interface
  feat(imx8ulp): add some delay before cmc1 access
  feat(imx8ulp): add a flag check for the ddr status
  fix(imx8ulp): add sw workaround for csi/hotplug test hang
  feat(imx8ulp): adjust the voltage when sys dvfs enabled
  feat(imx8ulp): enable the DDR frequency scaling support
  fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only
  feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID
  feat(imx8ulp): add memory region policy
  feat(imx8ulp): protect TEE region for secure access only
  feat(imx8ulp): add trusty support
  feat(imx8ulp): add OPTEE support
  feat(imx8ulp): update the upower config for power optimization
  feat(imx8ulp): allow RTD to reset APD through MU
  feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD
  feat(imx8ulp): add system power off support
  feat(imx8ulp): add APD power down mode(PD) support in system suspend
  feat(imx8ulp): add the basic support for idle & system suspned
  feat(imx8ulp): enable 512KB cache after resume on imx8ulp
  feat(imx8ulp): add the initial XRDC support
  feat(imx8ulp): allocated caam did for the non secure world
  feat(imx8ulp): add i.MX8ULP basic support
  build(changelog): add new scopes for nxp imx8ulp platform
  feat(scmi): add scmi sensor support

Change the names of some FWU metadata structure members to have them
align with the wording used in the corresponding specification. Use
the GUID type instead of UUID as the fields described in the
specification are GUIDs. Make corresponding changes to the code that
accesses these fields. No functional changes are introduced by the
patch.

Change-Id: Id3544ed1633811b0eeee2bf99477f9b7e6667044
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

The GPT partition uses GUID values for identification of partition
types and partitions. Change the relevant functions to use GUID values
instead of UUID's.

Change-Id: I30df66a8a02fb502e04b0285f34131b65977988e
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

In a few scenarios, there is a need to boot the platform from an
alernate bank which is not the active bank. Call the API
fwu_get_alernate_boot_bank() to select an alternate bank to boot the
platform from. Calling this API function might be required in a couple
of cases. One, in the unlikely scenario of the active bank being in an
invalid state, or if the number of times the platform boots in trial
state exceeds a pre-set count.

Also add a debug print that indicates the bank that
the platform is booting from.

Change-Id: I688406540e64d1719af8d5c121821f5bb6335c06
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

Add an API stm32_clear_fwu_trial_boot_cnt() function to clear the
trial state counter. This is called in the corner case scenario when
the active index is in an Invalid state, thus needing a reset of the
trial state counter.

Change-Id: I2980135da88d0d947c222655c7958b51eb572d69
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

Add a function fwu_get_alternate_boot_bank() to return a valid bank to
boot from. This function can be called by a platform to get an
alternate bank to try to boot the platform in the unlikely scenario of
the active bank being in an invalid state, or if the number of times
the platform boots in trial state exceeds a pre-set count.

Change-Id: I4bcd88e68e334c452882255bf028e01b090369d1
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

Add some sanity checks on the values read from the FWU metadata
structure. This ensures that values in the metadata structure are
inline with certain config symbol values.

Change-Id: Ic4415da9048ac3980f8f811ed7852beb90683f7d
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

The version 2 of the FWU metadata structure has a field bank_state in
the top level of the structure which can be used to check if a given
bank is in the either of Trial State, Accepted State, or in an Invalid
State. This is different from the binary states of Valid/Accepted
States that the bank could be in, as defined in the earlier version of
the specification.

Replace the fwu_is_trial_run_state() API with
fwu_get_active_bank_state() to get the state the current active bank
is in. The value returned by this API is then used by the caller to
take appropriate action.

Change-Id: I764f486840a3713bfe5f8e03d0634bfe09b23590
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

With version 2 of the FWU metadata structure, the state that a bank is
in can be obtained from the bank_state field in the top level
structure. Read the state of the active bank by referencing this field
directly, instead of making an API call.

Change-Id: Ib22c56acbe172923b1323c544801ded81f1598ec
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

The version 2 of the FWU metadata structure is designed such that the
information on the updatable images can be omitted from the metadata
structure. Add a configuration flag, PSA_FWU_METADATA_FW_STORE_DESC,
which is used to select whether the metadata structure has this
information included or not. It's value is set to 1 by default.

Change-Id: I4463a20c94d2c745ddb0b2cc8932c12d418fbd42
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

The latest version of the FWU specification [1] has changes to the
metadata structure. This is version 2 of the structure.

Primary changes include
 - bank_state field in the top level structure
 - Total metadata size in the top level structure
 - Image description structures now optional
 - Number of banks and images per bank values part of the structure

Make changes to the structure to align with version 2 of the structure
defined in the specification. These changes also remove support for
version 1 of the metadata structure.

[1] - https://developer.arm.com/documentation/den0118/latest/



Change-Id: I84b4e742e463cae92375dde8b4603b4a581d62d8
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

The version 2 of the FWU metadata structure is designed such that the
information on the updatable images can be omitted from the metadata
structure. Add a config flag, PSA_FWU_METADATA_FW_STORE_DESC, which is
used to select whether the metadata structure has this information
included or not. It's value is set to 1 by default.

Change-Id: Id6c99455db768edd59b0a316051432a900d30076
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

Update the links for accessing the FWU Multi Bank update specification
to point to the latest revision of the specification.

Change-Id: I25f35556a94ca81ca0a7463aebfcbc2d84595e8f
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the QEMU platform only.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I6188d73dd3f3c97f41bb25de543f8c46a972adf0

Cortex-X3 erratum 2372204 is a Cat B erratum that applies to revisions
r0p0 and r1p0. It is fixed in r1p1.

The workaround is to set bit[40] of CPUACTLR2_EL1 to disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest



Change-Id: Iad28f8625c84186fbd8049406d139d4f15c6e069
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

* changes:
  refactor(tc): reorder config variable defines
  refactor(tc): move DTB to start of DRAM

* changes:
  feat(el3-runtime): introduce UNDEF injection to lower EL
  feat(cpufeat): added few helper functions

For a feature to be used at lower ELs, EL3 generally needs to disable
the trap so that lower ELs can access the system registers associated
with the feature. Lower ELs generally check ID registers to dynamically
detect if a feature is present (in HW) or not while EL3 Firmware relies
statically on feature build macros to enable a feature.

If a lower EL accesses a system register for a feature that EL3 FW is
unaware of, EL3 traps the access and panics. This happens mostly with
EL2 but sometimes VMs can also cause EL3 panic.

To provide platforms with capability to mitigate this problem, UNDEF
injection support has been introduced which injects a synchronous
exception into the lower EL which is supposed to handle the
synchronous exception.

The current support is only provided for aarch64.

The implementation does the following on encountering sys reg trap

 - Get the target EL, which can be either EL2 or EL1
 - Update ELR_ELx with ELR_EL3, so that after UNDEF handling in lower EL
   control returns to original location.
 - ESR_ELx with EC_UNKNOWN
 - Update ELR_EL3 with vector address of sync exception handler with
   following possible causes
     - Current EL with SP0
     - Current EL with SPx
     - Lower EL using AArch64
 - Re-create SPSR_EL3 which will be used to generate PSTATE at ERET

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1b7bf6c043ce7aec1ee4fc1121c389b490b7bfb7

* changes:
  feat(gpt): validate CRC of GPT partition entries
  refactor(gpt): return header instead of part_lba

Following utility functions/bit definitions done
 - Write a helper function to return the presence of following features
    - FEAT_UAO
    - FEAT_EBEP
    - FEAT_SEBEP
    - FEAT_SSBS
    - FEAT_NMI
    - FEAT_PAN
 - Add definition of some missing bits of SPSR.
 - Add GCSCR_EL1 register encoding and accessor function.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifcead0dd8e3b32096e4ab810dde5d582a889785a

This change updates the Node Version Manager version file to the latest
long-term release version of Node.js, v20.11.1, and the Node.js Package
Manager package file to require Node.js version v20 or later.

Additionally, all Node.js modules have been updated, as some packages
required additional accommodations to be made compatible with this
version of Node.js.

As part of this, the `.commitlintrc.js` has been rewritten from CommonJS
to ECMAScript. There should be no impact on the behaviour of Commitlint,
but this was was a requirement to allow Commitlint to continue using it
for configuration.

Change-Id: I7043faabc516c58edda9e58848b0569e2158b271
Signed-off-by: Chris Kay <chris.kay@arm.com>

While loading partition entries, calculate CRC using tf_crc32() for each
entry to find the full CRC value of the partition entry array.

The start of the GPT partition entry array is located at the LBA
indicated by the partition entry array LBA field in the GPT header. The
size of the partition entry array is indicated by the size of partition
entry multiplied by the number of partition entries.

Compare the calculated CRC with the partition entry array CRC in the GPT
header, error out if the values do not match.

Change-Id: I4bfed8cf903125c1ef3fac2f0f4c0fb87d63aa78
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

Alter the function parameter to pass the full GPT header to be filled
instead of the starting LBA of the array of partion entries to
load_partition_gpt()

Change-Id: Ib3dde62d5b9996e74157714634bea748bd3b55aa
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

* changes:
  refactor(tc): correlate secure world addresses with platform_def
  feat(tc): add memory node in the device tree
  feat(tc): pass the DTB address to BL33 in R0
  feat(tc): add arm_ffa node in dts
  chore(tc): add dummy entropy to speed up the Linux boot
  feat(tc): choose the DPU address and irq based on the target
  feat(tc): add SCMI power domain and IOMMU toggles
  refactor(tc): move the FVP RoS to a separate file
  feat(tc): factor in FVP/FPGA differences
  feat(tc): introduce an FPGA subvariant and TC3 CPUs
  feat(tc): add TC3 platform definitions
  refactor(tc): sanitise the device tree
  feat(tc): add PMU entry
  feat(tc): allow booting from DRAM
  chore(tc): remove unused hdlcd
  feat(tc): add firmware update secure partition
  feat(tc): add spmc manifest with trusty sp
  refactor(tc): unify all the spmc manifests
  feat(arm): add trusty_sp_fw_config build option
  fix(tc): do not enable MPMM and Aux AMU counters always
  fix(tc): correct interrupts
  feat(tc): interrupt numbers for `smmu_700`
  feat(tc): enable gpu/dpu scmi power domain and also gpu perf domain

Add the maintainers for NXP i.MX8ULP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ifc5f86ad6eb7288ef28765311fc3b1ff48031df5

Add i.MX8ULP platform introduction.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Idc16bcf5b23542f8a1f394a474309239ddcb9685

the mmap region num is not enough for the mmap regions,
so increase it, increase the xlat_table num too.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2a2515b291e96cc12398a2c2c526351342811fff

below commit mapped 16 MB memory from the start of DRAM(0x80000000),
which may have conflict with the shared memory used by Trusty OS:
  LF-8819: plat: imx8ulp: ddrc switch auto low power and software interface

change the mapped memory to 'vdev0buffer' reserved memory (0x8ff00000)
to avoid memory conflict. This commit also bumps the XTLB tables
to avoid mapping failure.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Change-Id: I1a7af958af47e3fc9955d0a80d1649971e843eab

Enable switch between DDRC Auto low power and software/hardware
control modes DDRC Auto low-power mode is used when system is
active, software/hardware control mode is used when going into
suspend. Enable switching between Auto mode and SW/HW mode in
enter/exit retention routines.

Set LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 Max setting to allow
LPDDR_EN_CLKGATE reload LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 to
exit retention mode

Signed-off-by: Pascal Mareau <pascal.mareau@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Hongting Ting <hongting.dong@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3c4b6f7bc6ca02649ff27cd3d9a0c50dab3a3ad0

When resume from APD sleep mode, need to add a small delay
before accessing the CMC1 register.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ic8acdf58a3bf82b1791e7ae7f173f8c94c56b49d

for some user case, the ddr may need to be controlled
by RTD side to save power, when APD resume from low
power mode, it should wait ddr is ready for access.
currently we use a GPR in SIM_RTD_SEC as a flag to
indicate when the DDR is for access, non-zero value
means the DDR can be access from APD.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6fb0cc17a040d803a597304620202423f646f294

When doing CSI stress test after cpu hotplug, sometimes, system
will hang in CSI test. After some debug, we find that if slow
down the APD NIC frequency before power on the offline CPU,
the issue is gone. For now, just add such SW workaround.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I39a49efc382fbebf46e1ff15c93d506bd5f6bec1